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Commit db025004 authored by Angus Ainslie's avatar Angus Ainslie
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Merge branch 'load-m4-from-hardware-boot-partition' into 'devkit-wip' 

Load the M4 code from the same eMMC partition the SPL booted from

See merge request Librem5/uboot-imx!4
parents bb3861a8 35cce237
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Showing with 135 additions and 122 deletions
board/emcraft/imx8m_som/ddr/lpddr4/helper.c
View file @ db025004
......@@ -273,6 +273,53 @@ void M4_load_firmware( enum fw_type type )
#endif
}
static struct mmc *prepare_mmc_boot_device(void)
{
struct mmc *mmc;
int err;
int boot_device;
int boot_mode;
__maybe_unused int part;
printf("Finding MMC device\n");
boot_device = spl_boot_device();
boot_mode = spl_boot_mode(boot_device);
err = spl_mmc_find_device(&mmc, boot_device);
if (err) {
printf("spl: mmc find device failed with error: %d\n", err);
return NULL;
}
err = mmc_init(mmc);
if (err) {
printf("spl: mmc init failed with error: %d\n", err);
return NULL;
}
/* Switch to the same partition as where the SPL is stored */
if (boot_mode == MMCSD_MODE_EMMCBOOT) {
int part;
part = (mmc->part_config >> 3) & PART_ACCESS_MASK;
if (part == 7)
part = 0;
printf("spl: switching to mmc hwpartition %d\n", part);
if (CONFIG_IS_ENABLED(MMC_TINY)) {
err = mmc_switch_part(mmc, part);
} else {
err = blk_dselect_hwpart(mmc_get_blk_desc(mmc), part);
}
if (err) {
printf("spl: mmc partition switch failed\n");
return NULL;
}
}
return mmc;
}
void start_M4(void)
{
struct mmc *mmc;
......@@ -280,8 +327,7 @@ void start_M4(void)
void *vect_buffer = (void *)TCML_BASE;
void *buffer = (void *)OCRAM_BASE;
uint32_t status, reg, stack, pc;
int err, count;
int boot_device;
int count;
#if 0
/* use this wait to stop the code for the OpenOCD debugger */
volatile int i = 0;
......@@ -294,71 +340,54 @@ void start_M4(void)
printf("Setting up AIPS\n");
init_aips();
printf("Finding MMC device\n");
mmc = prepare_mmc_boot_device();
if (!mmc)
return;
boot_device = spl_boot_device();
printf("Disabling Cortex M4 clock\n");
clock_enable(CCGR_M4, 0);
if(0 == (err = spl_mmc_find_device(&mmc, boot_device)))
{
printf("Getting block device\n");
block_dev = mmc_get_blk_desc(mmc);
printf("Loading Cortex M4 firmware loader\n");
/* From 2k copy - blocks are 512 bytes each */
blk_dread(block_dev, 4, 64, buffer);
printf("Loading Cortex M4 exception vectors\n");
blk_dread(block_dev, 4, 1, vect_buffer);
err = mmc_init(mmc);
if (err) {
printf("spl: mmc init failed with error: %d\n", err);
}
else
{
printf("Disabling Cortex M4 clock\n");
clock_enable(CCGR_M4, 0);
printf("Getting block device\n");
block_dev = mmc_get_blk_desc(mmc);
printf("Loading Cortex M4 firmware loader\n");
/* From 2k copy - blocks are 512 bytes each */
blk_dread(block_dev, 4, 64, buffer);
printf("Loading Cortex M4 exception vectors\n");
blk_dread(block_dev, 4, 1, vect_buffer);
printf("Starting Cortex M4 core\n");
stack = *(u32 *)buffer;
pc = *(u32 *)(buffer + 4);
/* Set the stack and pc to M4 bootROM */
writel(stack, M4_BOOTROM_BASE_ADDR);
writel(pc, M4_BOOTROM_BASE_ADDR + 4);
printf("Enabling Cortex M4 clock\n");
clock_enable(CCGR_M4, 1);
printf("reset M4 core\n");
reg = readl(SRC_M4RCR);
writel((reg & ~0xF)| 0xa, SRC_M4RCR);
status = readl(TCMU_ST_M4);
for(count = 0; count < 50000; count++)
{
status = readl(TCMU_ST_M4);
if( status == ST_READY )
break;
udelay( 10 );
}
if(status == ST_READY) {
printf("Cortex M4 ready\n");
}
else
{
printf("Cortex M4 NOT ready\n");
}
printf("Starting Cortex M4 core\n");
}
}
else
stack = *(u32 *)buffer;
pc = *(u32 *)(buffer + 4);
/* Set the stack and pc to M4 bootROM */
writel(stack, M4_BOOTROM_BASE_ADDR);
writel(pc, M4_BOOTROM_BASE_ADDR + 4);
printf("Enabling Cortex M4 clock\n");
clock_enable(CCGR_M4, 1);
printf("reset M4 core\n");
reg = readl(SRC_M4RCR);
writel((reg & ~0xF)| 0xa, SRC_M4RCR);
status = readl(TCMU_ST_M4);
for(count = 0; count < 50000; count++)
{
printf("spl: mmc find device failed with error: %d\n", err);
status = readl(TCMU_ST_M4);
if( status == ST_READY )
break;
udelay( 10 );
}
if(status == ST_READY) {
printf("Cortex M4 ready\n");
} else {
printf("Cortex M4 NOT ready\n");
}
}
#if defined(CONFIG_M4_LOAD_DDR_TRAINING)
void ddr_load_train_code(enum fw_type type)
{
struct mmc *mmc;
......@@ -366,78 +395,62 @@ void ddr_load_train_code(enum fw_type type)
void *vect_buffer = (void *)TCML_BASE;
void *buffer = (void *)OCRAM_BASE;
uint32_t status, reg, stack, pc;
int err, count;
int boot_device;
int count;
#if defined(CONFIG_M4_LOAD_DDR_TRAINING)
printf("Finding MMC device\n");
mmc = prepare_mmc_boot_device();
if (!mmc)
return;
boot_device = spl_boot_device();
printf("Disabling Cortex M4 clock\n");
clock_enable(CCGR_M4, 0);
printf("Getting block device\n");
block_dev = mmc_get_blk_desc(mmc);
printf("Loading Cortex M4 firmware loader\n");
/* From 2k copy - blocks are 512 bytes each */
blk_dread(block_dev, 4, 64, buffer);
printf("Loading Cortex M4 exception vectors\n");
blk_dread(block_dev, 4, 1, vect_buffer);
printf("Starting Cortex M4 core\n");
stack = *(u32 *)buffer;
pc = *(u32 *)(buffer + 4);
/* Set the stack and pc to M4 bootROM */
writel(stack, M4_BOOTROM_BASE_ADDR);
writel(pc, M4_BOOTROM_BASE_ADDR + 4);
if(0 == (err = spl_mmc_find_device(&mmc, boot_device)))
printf("Enabling Cortex M4 clock\n");
clock_enable(CCGR_M4, 1);
printf("reset M4 core\n");
reg = readl(SRC_M4RCR);
writel((reg & ~0xF)| 0xa, SRC_M4RCR);
status = readl(TCMU_ST_M4);
for(count = 0; count < 50000; count++)
{
status = readl(TCMU_ST_M4);
if( status == ST_READY )
break;
udelay( 10 );
}
err = mmc_init(mmc);
if (err) {
printf("spl: mmc init failed with error: %d\n", err);
}
else
{
printf("Disabling Cortex M4 clock\n");
clock_enable(CCGR_M4, 0);
printf("Getting block device\n");
block_dev = mmc_get_blk_desc(mmc);
printf("Loading Cortex M4 firmware loader\n");
/* From 2k copy - blocks are 512 bytes each */
blk_dread(block_dev, 4, 64, buffer);
printf("Loading Cortex M4 exception vectors\n");
blk_dread(block_dev, 4, 1, vect_buffer);
printf("Starting Cortex M4 core\n");
stack = *(u32 *)buffer;
pc = *(u32 *)(buffer + 4);
/* Set the stack and pc to M4 bootROM */
writel(stack, M4_BOOTROM_BASE_ADDR);
writel(pc, M4_BOOTROM_BASE_ADDR + 4);
printf("Enabling Cortex M4 clock\n");
clock_enable(CCGR_M4, 1);
printf("reset M4 core\n");
reg = readl(SRC_M4RCR);
writel((reg & ~0xF)| 0xa, SRC_M4RCR);
status = readl(TCMU_ST_M4);
for(count = 0; count < 50000; count++)
{
status = readl(TCMU_ST_M4);
if( status == ST_READY )
break;
udelay( 10 );
}
if(status == ST_READY) {
printf("Cortex M4 ready\n");
}
else
{
printf("Cortex M4 NOT ready\n");
}
//if( boot_M4() == ST_READY )
M4_load_firmware( type );
}
if(status == ST_READY) {
printf("Cortex M4 ready\n");
}
else
{
printf("spl: mmc find device failed with error: %d\n", err);
printf("Cortex M4 NOT ready\n");
}
#else
//if( boot_M4() == ST_READY )
M4_load_firmware( type );
}
#else /* !defined(CONFIG_M4_LOAD_DDR_TRAINING) */
void ddr_load_train_code(enum fw_type type)
{
old_ddr_load_train_code(type);
#endif
}
#endif
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