Commit ea920467 authored by Ye Li's avatar Ye Li Committed by Jason Liu
Browse files

MLK-15289 imx8m: Change USDHC1/2 clocks to 200Mhz



The USDHC uses default clock root OSC 25Mhz, this causes SD/eMMC reading
very slowly.
This patch changes the USDHC IP/BUS clock to 200Mhz.
Signed-off-by: default avatarYe Li <ye.li@nxp.com>
Reviewed-by: default avatarPeng Fan <peng.fan@nxp.com>
parent 59e5dade
......@@ -551,9 +551,9 @@ int clock_init()
*/
clock_enable(CCGR_USDHC1, 0);
clock_enable(CCGR_USDHC2, 0);
clock_set_target_val(NAND_USDHC_BUS_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0));
clock_set_target_val(USDHC1_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0));
clock_set_target_val(USDHC2_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0));
clock_set_target_val(NAND_USDHC_BUS_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(3));
clock_set_target_val(USDHC1_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1) | CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
clock_set_target_val(USDHC2_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1) | CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
clock_enable(CCGR_USDHC1, 1);
clock_enable(CCGR_USDHC2, 1);
......
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment