- 16 Oct, 2019 1 commit
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Angus Ainslie (Purism) authored
Signed-off-by:
Angus Ainslie (Purism) <angus@akkea.ca>
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- 14 Oct, 2019 1 commit
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Angus Ainslie (Purism) authored
enable the SPI bus and NOR flash Signed-off-by:
Angus Ainslie (Purism) <angus@akkea.ca>
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- 11 Oct, 2019 1 commit
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Angus Ainslie (Purism) authored
Signed-off-by:
Angus Ainslie (Purism) <angus@akkea.ca>
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- 06 Oct, 2019 1 commit
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Angus Ainslie authored
Signed-off-by:
Angus Ainslie <angus@akkea.ca>
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- 02 Oct, 2019 1 commit
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Angus Ainslie authored
Signed-off-by:
Angus Ainslie <angus@akkea.ca>
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- 28 Sep, 2019 1 commit
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Angus Ainslie (Purism) authored
Signed-off-by:
Angus Ainslie (Purism) <angus@akkea.ca>
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- 24 May, 2019 1 commit
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Ye Li authored
Update thermal node properties, i2c pinmux, usdhc pinmux, uart nodes, qspi node, gpmi/apbh-dma nodes and alias. Signed-off-by:
Ye Li <ye.li@nxp.com>
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- 01 Jan, 2019 1 commit
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Peng Fan authored
Add i.MX8MQ EVK support. SPL will initialize ddr and load ddr phy firmware. Then loading FIT image, ATF to OCRAM, U-Boot and DTB to DRAM. The boot log with Arm trusted firmware console enabled: " U-Boot SPL 2018.11-00142-g9ae14e7274 (Nov 20 2018 - 18:13:16 +0800) PMIC: PFUZE100 ID=0x10 Normal Boot Trying to boot from MMC2 NOTICE: Configureing TZASC380 NOTICE: BL31: v1.5(release):p9.0.0_1.0.0-beta-20180928-8-ge09c4b62-dirty NOTICE: BL31: Built : 09:28:54, Nov 8 2018 lpddr4 swffc start NOTICE: sip svc init U-Boot 2018.11-00142-g9ae14e7274 (Nov 20 2018 - 18:13:16 +0800) CPU: Freescale i.MX8MQ rev2.0 at 1000 MHz Reset cause: POR Model: Freescale i.MX8MQ EVK DRAM: 3 GiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 In: serial Out: serial Err: serial Net: Warning: ethernet@30be0000 using MAC address from ROM eth0: ethernet@30be0000 Hit any key to stop autoboot: 0 " Signed-off-by:
Peng Fan <peng.fan@nxp.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
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