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NAND module is pin conflict with SD/eMMC on i.MX8QXP ARM2 board,
add new config to disable SD/eMMC when booting from NAND.
Signed-off-by: Han Xu <han.xu@nxp.com>

enable the GPMI NAND driver for i.MX8, the major changes

- register defination for i.mx8
- Makefile change for misc.c
- DMA structure must be 32bit address
Signed-off-by: Han Xu <han.xu@nxp.com>

Enable pinctrl/dm mmc/dm i2c/dm regulator and pmic.
Since we do not enable DM for SPL, so move non dm
code to spl file.
Signed-off-by: Peng Fan <peng.fan@nxp.com>

Add dts for i.mx8mq evk board.
dts kernel commit f66fac9f84.
Signed-off-by: Peng Fan <peng.fan@nxp.com>

This patch enables the power domain driver for i.MX8QM and QXP boards in defconfig files.
The devices with using DM driver will be powered on automatically by DM framework. So
we remove the power relevant codes for them.
For devices with non-DM drivers, we updates the board/SoC codes to use power domain driver API.
So that we can use power domain driver to manage them.

The only exceptions are:
1. UART0 at board_early_f, this is very early stage, that power domain is not ready.
2. Power up secondary cores and M4 cores. These resources are not peripherals and
   are not in power domain tree.

Additional, benefiting from power domain driver, We have implemented the function "power_off_pd_devices"
to power off all active devices. No need to explicitly power off them in board_quiesce_devices.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>

Sync the DTSi files and binding files with latest kernel commit:
"commit 2ce220ede08c0802a12459877ae134812ddda20b"

Some extra modifications:
1. Add "power-domains" property to all GPIO nodes and flexspi node, since
   they miss to add it.
2. Add "simple-bus" compatible strings to imx8qm-pm node.
3. Rename nodes "i2c0_mipi_lvds0" and "i2c0_mipi_lvds1"
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>

Sync the DTSi files and binding files with latest kernel commit:
"commit 2ce220ede08c0802a12459877ae134812ddda20b"

Some extra modifications:
1. Add "power-domains" property to all GPIO nodes and flexspi node, since
they miss to add it.
2. Fix the wrong SATA PD name, should be "PD_HSIO_SATA_0".
3. Add "simple-bus" compatible strings to imx8qm-pm node.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>

Add the power domain DM driver for i.MX8, that it depends on the DTB
power domain trees to generate the power domain provider devices. Users
needs add power domain trees with property "compatible = "nxp,imx8-pd";"

- When power on one PD device, the driver will power on its ancestor PD devices
in power domain tree.

- When power off on PD device, the driver will check its child PD devices first,
only all child PD devices are off, then power off the current PD device. Then the
driver checks sibling PD devices. If sibling PD devices are off, then it will power
off parent PD device.

- There is no counter maintained in this driver, but a state to hold current on/off
state. So the request and free functions are empty.

- The power domain implemetation in i.MX8 DTB set the "#power-domain-cells" to 0, so
there is no ID binding with each PD device. We don't use "id" variable in
struct power_domain. At same time, we have to set of_xlate to empty to bypass standard
of_xlate in uclass driver.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>

Support MFG.
1. When ROM jumps to SPL, SPL saves ROM context. After SPL successfully
   initialize DRAM, SPL will restore ROM and context and back to ROM.
   During this flow, SPL does not do any USB configuration to avoid
   breaking the connect between ROM and Host PC, because we rely on
   ROM to continue serial download with Host.
2. Add MFG env to support kernel boot correctly.
Signed-off-by: Peng Fan <peng.fan@nxp.com>

This patch enables the pinctrl driver for i.MX8QXP ARM2 and MEK boards.
For DM enabled driver, the iomux pins can be set by pinctrl driver. So
the board codes don't need to set iomux explicitly for these DM enabled modules.

Also update the DTS file for i2c pins settings.
Signed-off-by: Ye Li <ye.li@nxp.com>

This patch enables the pinctrl driver for i.MX8QM ARM2 board.
For DM enabled driver, the iomux pins can be set by pinctrl driver. So
the board codes don't need to set iomux explicitly for these DM enabled
modules.

Also update the DTS file for some module's pins settings.
Signed-off-by: Ye Li <ye.li@nxp.com>

Before starting the kernel, need to check if the enabled nodes (resources) in FDT
are owned by current partition.  If it is not owned, need to disable it because A core
can't access it.
We use the node's power-domain property to get the PD node which has the SCFW resource
id in its reg property. Then we can check it with SCFW.
Signed-off-by: Ye Li <ye.li@nxp.com>

Since the memory regions assigned to u-boot partition is dynamically set by
ATF and SCD. We have to setup MMU pagetables according to the owned memory
regions, not set it for unassigned memory.
Signed-off-by: Ye Li <ye.li@nxp.com>

Discard the ATF memory region from MMU table. ATF region is
protected by TZASC, however U-Boot runs in non-secure EL2,
we should not map the ATF region in U-Boot.
Signed-off-by: Peng Fan <peng.fan@nxp.com>

Fix SD3_VCC power rail enablement on DM MMC build
Add in pin control hog group MX6QDL_PAD_GPIO_18__SD3_VSELECT
pad for early power on of SD3_VCC power rail.
Add cd-gpio property.
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>

We assign the DDR memory from 0x88000000 to 0x8FFFFFFF to M4 on QM and QXP.
The M4 can allocate this memory by two ways, in SCD or u-boot.

There are 3 things needed to change in u-boot:
1. Move the u-boot INIT SP address to first 128M memory to avoid conflict with M4 memory.

2. The memory regions may be allocated in SCD or ATF. So we can't staticly set the memory
   bank information in u-boot, need to get it from owned memory regions.

3. u-boot addes the memory reserve node to DTB to pass the info to kernel, no matter
   the M4 memory is reserved in SCD or u-boot. So kernel won't access M4 reserved memory.

The codes for M4 resources and memory regions allocated by u-boot will be added
later when they are finalized.
Signed-off-by: Ye Li <ye.li@nxp.com>

Enable the CONFIG_SUPPORT_EMMC_BOOT, so that for eMMC boot SPL can switch
to boot partition for u-boot.img loading.
Signed-off-by: Ye Li <ye.li@nxp.com>

Add the board file, head file, build config and DTS for i.MX8QXP MEK.
Enabled SD/eMMC, FlexSPI, UART, LPI2C, I2C MUX, IO EXP and Ethernet.

DTS is based on kernel patch (commit 86203e3c136836d6b01d5e00ac52c561014f1cab),
and add support for i2c mux, ioexp, second ethernet on base board and flexspi.
Signed-off-by: Ye Li <ye.li@nxp.com>

Default enable TZC380.
Signed-off-by: Peng Fan <peng.fan@nxp.com>

Refine mmu table. Map TCML/TCMU as non-cachable.
Remove the map of CAAM secure ram and OCRAM_S.
Signed-off-by: Peng Fan <peng.fan@nxp.com>

To page mapping the lowest 2 bits needs to be 0x3.
If not fix this, the final lowest 3 bits for page mapping is 0x1
which is marked as reserved.
Signed-off-by: Peng Fan <peng.fan@nxp.com>

    "
    commit a645f3c4c529e1f8cc5a624a047a3af56cfd39e1
    Author: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>
    Date:   Thu Jun 29 15:21:53 2017 -0500

        Turn off all HDMI-TX clocks by default. This is required for setting
        the rate of the DIG PLL.
        Add code to enable/disable the correct clocks before SECO accesses the HD
Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>
    "
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>

Add common functions for LVDS/DC setup, video framebuffer init/disable,
LVDS to HDMI card settings, etc. Refactor it from video_imxdpuv1.c.
1. Add power, clocks, PLL relevant setup for LVDS and DC.
2. Configure the LVDS and its PHY settings for the display format and pixel link.
3. Setup the LVDS to HDMI card.
4. Implement the video_hw_init by calling DC driver API to output data to
   specified display panel.
Signed-off-by: Oliver Brown <oliver.brown@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>

Implement mmc_get_env_dev
Signed-off-by: Peng Fan <peng.fan@nxp.com>

Support more boot device.
Signed-off-by: Peng Fan <peng.fan@nxp.com>

ROM will update ROM_SW_INFO according to boot media, so U-Boot could
reuse that info.
Signed-off-by: Peng Fan <peng.fan@nxp.com>

Power down wdog counter to avoid reset after 16 seconds.
Add set_wdog_set to configure wcr to use WDOG_B reset.
Configure iomux to output WDOG_B to reset system.
Build watchdog driver for imx8mq.
Signed-off-by: Peng Fan <peng.fan@nxp.com>

Enforce no-pic for SPL and normal U-Boot. If not, there
will be .got and .got.plt sections for dynamic link.
Signed-off-by: Peng Fan <peng.fan@nxp.com>

Add get_boot_device and get_board_serial in soc.c.
Add is_recovery_key_pressing function definition
Use CONFIG_USB_GADGET and CONFIG_FSL_FASTBOOT to separate the usb related code
in the f_fastboot.c.The CONFIG_USB_FUNCTION_FASTBOOT should be defined So the
boota can work normally.

Change-Id: I6c0d3851ba28b147d0da310485a06f102de5a813
Signed-off-by: Zhang Bo <bo.zhang@nxp.com>

Reuse imx-common code for cpuinfo.
Add a dummy crm_regs.h file, becasue imx-common code includes it.
Add src register map for i.MX8M.
Signed-off-by: Peng Fan <peng.fan@nxp.com>

Add board support for imx6dl pico pi

Change-Id: I2003b1713122580c514a98759587023fef5deb3a
Signed-off-by: fang hui <hui.fang@nxp.com>

To avoid violating GPL license, we can't static link the DDR PHY FW into
uboot binary, so change to attach the FW images with u-boot binary.

Remove the codes and link scripts for static linking the FW in sections.
Signed-off-by: Ye Li <ye.li@nxp.com>

* add board support for android and android things.
  mx6ul_nxpu_iopb, pico-6ul, pico-imx7d, aquila-6ul
  reorganize the Kconfig, and fix the redefine issue.
* add android configure into configure-while
* add a common file mx_android_common.h
  it will be included by android and android things.
  defconfig only include ANDROID_THINGS_SUPPORT or ANDROID_SUPPORT
* move partition_table_valid into f_fastboot.c.
  it's a common code.
* add invalidate_dcache_range in fixed order.
  It will have salt invalid issue if we do not add it in order
* add display for pico-7d.

Change-Id: I6f8a4876c2f8bbd098034d1e3f53033109300bca
Signed-off-by: zhang sanshan <sanshan.zhang@nxp.com>

Fix issue for API changed from v2017.
porting below patch from v2016.
commit 44834fd12f60a090e3d10ab6f84a75460894d49d

Change-Id: Ifaf0b86dd29648f9150646f00f54502676df9013
Signed-off-by: zhang sanshan <sanshan.zhang@nxp.com>

The USDHC uses default clock root OSC 25Mhz, this causes SD/eMMC reading
very slowly.
This patch changes the USDHC IP/BUS clock to 200Mhz.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>

Fix the build warning below:

arch/arm/cpu/armv8/imx8m/clock.c: In function ‘decode_frac_pll’:
arch/arm/cpu/armv8/imx8m/clock.c:37:36: warning: variable ‘pll_newdiv’
set but not used [-Wunused-but-set-variable]
 u32 divr_val, divq_val, divf_val, pll_newdiv, divff, divfi;
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>

When compiling with android toolchain, there is an instruction
"str     q0, [x8],#16", but x8 is not 16bytes aligned,
this instruction will trigger sync abort.

So, following Linux kernel, only use general regs for arm64.
If not, compiler may use simd registers Q[x]. We need to avoid
using simd registers in U-Boot, because load/store Q[x] has
restriction that 128bits aligned when str/ldr.
Signed-off-by: Peng Fan <peng.fan@nxp.com>

Add i.MX8M EVK board support.
The drivers are not switched to use driver model now.
SPL is used to initialize DDR Controller and DDR PHY, then
load u-boot.img from SD to DRAM.
ATF and PHY FW bin are included.
Signed-off-by: Peng Fan <peng.fan@nxp.com>

Add ddr register memory map
Signed-off-by: Peng Fan <peng.fan@nxp.com>

Add ddr phy fw section in SPL link file.
Also when objcopy, do not ignore the firmware section.
Signed-off-by: Peng Fan <peng.fan@nxp.com>