1. 05 Sep, 2018 1 commit
    • Ye Li's avatar
      MLK-19433-2 imx8mq: Get chip rev for B1 revision · 9dba7a4d
      Ye Li authored
      
      
      The mscale B1 uses OCOTP_HW_OCOTP_READ_FUSE_DATA register for chip id.
      It returns a magic number 0xff0055aa.
      Update get_cpu_rev to support this way, also enable OCOTP clock to allow
      access OCOTP register.
      Signed-off-by: default avatarYe Li <ye.li@nxp.com>
      (cherry picked from commit 866631c2140b9352c6f74ec36d1a51fea40c0445)
      9dba7a4d
  2. 03 Sep, 2018 1 commit
    • Ye Li's avatar
      MLK-19355 imx8mm: Enable sec_debug clock in SPL · c738b76a
      Ye Li authored
      
      
      ipg_stop from GPC is not connected to WDOG directly, the sec_debug clock is
      used to sample the ipg_stop from GPC. So when this clock is off, ipg_stop input
      of WDOG can’t assert, WDOG will fail to stop in DSM mode.
      Enable this clock forever in SPL, so other SW don't need to touch it.
      Signed-off-by: default avatarYe Li <ye.li@nxp.com>
      Tested-by: default avatarBai Ping <ping.bai@nxp.com>
      (cherry picked from commit 1da6c9b3a837d15c25086af449462d5e8b56c290)
      c738b76a
  3. 28 Aug, 2018 1 commit
    • Zhang Bo's avatar
      MA-12536[Android] Enable RTC for imx8m in uboot · b6a1a19c
      Zhang Bo authored
      
      
      Enable RTC in bootloader to avoid rtc time less than jiffies time
      when linux first bootup after RTC lose power.
      It will cause the issue as
      MA-9554[Android_6DL_SD]RTC: Sometimes the RTC reset to the initial
      time 1970 after softare reboot the first time. 40%
      
      Change-Id: I0c87180640be98a2c928a30c6949f91f4515844d
      Signed-off-by: default avatarZhang Bo <bo.zhang@nxp.com>
      b6a1a19c
  4. 21 Aug, 2018 1 commit
  5. 16 Aug, 2018 1 commit
  6. 08 Aug, 2018 1 commit
    • Ye Li's avatar
      MLK-19159 imx8mm_evk: Fix build break for flexspi defconfig · 42d21af4
      Ye Li authored
      
      
      The flexspi defconfig uses CONFIG_ENV_IS_IN_SPI_FLASH not CONFIG_ENV_IS_IN_MMC.
      So when fastboot is enabled for flexspi, the build break happens.
      
      drivers/usb/gadget/built-in.o: In function `board_fastboot_setup':
      /home/leyoen/Workspace/uboot-imx/drivers/usb/gadget/f_fastboot.c:1539: undefined reference to `mmc_get_env_dev'
      drivers/usb/gadget/built-in.o: In function `_fastboot_setup_dev':
      /home/leyoen/Workspace/uboot-imx/drivers/usb/gadget/f_fastboot.c:1260: undefined reference to `mmc_get_env_dev'
      drivers/usb/gadget/built-in.o: In function `get_single_var':
      /home/leyoen/Workspace/uboot-imx/drivers/usb/gadget/f_fastboot.c:2935: undefined reference to `mmc_get_env_dev'
      drivers/usb/gadget/built-in.o: In function `bcb_rw_block':
      /home/leyoen/Workspace/uboot-imx/drivers/usb/gadget/bcb.c:120: undefined reference to `mmc_get_env_dev'
      
      Fix the issue by decoupling mmc_get_env_dev function with CONFIG_ENV_IS_IN_MMC
      Signed-off-by: default avatarYe Li <ye.li@nxp.com>
      (cherry picked from commit 2716f9a325681737593b3a6e79f94576a35067c2)
      42d21af4
  7. 20 Jul, 2018 1 commit
  8. 19 Jul, 2018 1 commit
  9. 13 Jul, 2018 1 commit
  10. 06 Jul, 2018 1 commit
  11. 04 Jul, 2018 1 commit
  12. 22 Jun, 2018 2 commits
    • Ye Li's avatar
      MLK-18639-3 imx8mm_val: Add board codes for iMX8MM DDR4 validation board · 60454847
      Ye Li authored
      
      
      Add SPL/u-boot board codes and DDR4 settings for iMX8MM DDR4 validation board.
      DDR overnight stress test is passed.
      
      Supported modules:
          SD/eMMC, I2C, ENET, Flexspi, UART and USB.
      
      Build config:
          imx8mm_ddr4_val_defconfig
      Signed-off-by: default avatarYe Li <ye.li@nxp.com>
      60454847
    • Ye Li's avatar
      MLK-18639-1 imx8mm: clock: Add API to enable/disable DDR bypass clock · 323b7377
      Ye Li authored
      
      
      The DRAM PLL generates clock to both DRAM controller & PHY, from 166.7MHz to 800MHz.
      So it can't be used when we need lower DDR frequency.
      The DRAM PHY supports a bypass mode to allow lower frequency operation from DDR-50 to
      DDR-666. In this mode, the PLL inside PHY is disabled, the PHY clock is provided externally
      as BypassPclk which is generated from dram_alt_clk_root.
      
      We add APIs for this bypass mode, to support frequencies for DDR-100, DDR-250 and DDR-400,
      which are needed when training DDR4.
      Signed-off-by: default avatarYe Li <ye.li@nxp.com>
      323b7377
  13. 22 May, 2018 1 commit
  14. 18 May, 2018 2 commits
  15. 11 May, 2018 1 commit
  16. 10 May, 2018 8 commits
  17. 12 Apr, 2018 1 commit
  18. 28 Feb, 2018 1 commit
  19. 13 Feb, 2018 1 commit
  20. 15 Dec, 2017 1 commit
  21. 08 Dec, 2017 2 commits
  22. 04 Dec, 2017 1 commit
  23. 30 Nov, 2017 1 commit
  24. 24 Nov, 2017 1 commit
  25. 22 Nov, 2017 2 commits
  26. 20 Nov, 2017 1 commit
  27. 16 Nov, 2017 1 commit
  28. 13 Nov, 2017 2 commits