/* * Copyright (C) 2016 Freescale Semiconductor, Inc. * Copyright 2017 NXP * Copyright (C) 2018 EmCraft Systems * * SPDX-License-Identifier: GPL-2.0+ */ /dts-v1/; #include "fsl-imx8mq.dtsi" / { model = "Librem 5"; compatible = "purism,librem5", "fsl,imx8mq"; chosen { bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200"; stdout-path = &uart1; }; regulators { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <0>; reg_usdhc2_vmmc: usdhc2_vmmc { compatible = "regulator-fixed"; regulator-name = "VSD_3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; enable-active-high; }; }; pwmleds { compatible = "pwm-leds"; ledpwm2 { label = "PWM2"; pwms = <&pwm2 0 50000>; max-brightness = <255>; }; }; }; &iomuxc { pinctrl-names = "default"; imx8m-som { pinctrl_i2c1: i2c1grp { fsl,pins = < MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000003f MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000003f >; }; pinctrl_i2c2: i2c2grp { fsl,pins = < MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000001f MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000001f >; }; pinctrl_i2c3: i2c3grp { fsl,pins = < MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000001f MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000001f >; }; pinctrl_i2c4: i2c4grp { fsl,pins = < MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x4000003f MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x4000003f >; }; pinctrl_ecspi1: ecspi1grp { fsl,pins = < MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x82 MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 >; }; pinctrl_pwm1: pwm1grp { fsl,pins = < MX8MQ_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x83 /* MOTO */ >; }; pinctrl_pwm2: pwm2grp { fsl,pins = < MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x16 /* LED_B */ >; }; pinctrl_pwm3: pwm3grp { fsl,pins = < MX8MQ_IOMUXC_SPDIF_TX_PWM3_OUT 0x16 /* LED_R */ >; }; pinctrl_pwm4: pwm4grp { fsl,pins = < MX8MQ_IOMUXC_SAI3_MCLK_PWM4_OUT 0x16 /* LED_G */ >; }; pinctrl_uart1: uart1grp { fsl,pins = < MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x79 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x79 >; }; pinctrl_uart3: uart3grp { fsl,pins = < MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x79 MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x79 MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x79 MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x79 MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x19 >; }; pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 >; }; pinctrl_usdhc1_100mhz: usdhc1grp100mhz { fsl,pins = < MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 >; }; pinctrl_usdhc1_200mhz: usdhc1grp200mhz { fsl,pins = < MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8f MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcf MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcf MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcf MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcf MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcf MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcf MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcf MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcf MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcf MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8f MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 >; }; pinctrl_usdhc2_gpio: usdhc2grpgpio { fsl,pins = < MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 /* WIFI_nRST */ >; }; pinctrl_usdhc2: usdhc2grp { fsl,pins = < MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 >; }; pinctrl_usdhc2_100mhz: usdhc2grp100mhz { fsl,pins = < MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 >; }; pinctrl_usdhc2_200mhz: usdhc2grp200mhz { fsl,pins = < MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8f MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcf MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcf MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcf MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcf MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcf MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 >; }; pinctrl_sai2: sai2grp { fsl,pins = < MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6 >; }; pinctrl_wdog: wdoggrp { fsl,pins = < MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 >; }; }; }; &i2c1 { clock-frequency = <100000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; }; &i2c2 { clock-frequency = <100000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; }; &i2c3 { clock-frequency = <100000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; }; &i2c4 { clock-frequency = <100000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c4>; status = "okay"; }; &ecspi1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; flash0: winbond@0 { reg = <0>; #address-cells = <1>; #size-cells = <1>; compatible = "spi-flash"; spi-max-frequency = <29000000>; }; }; &pwm2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm2>; status = "okay"; }; &uart1 { /* console */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; assigned-clocks = <&clk IMX8MQ_CLK_UART1_SRC>; assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; status = "okay"; }; &lcdif { status = "okay"; disp-dev = "mipi_dsi_northwest"; display = <&display0>; display0: display@0 { bits-per-pixel = <24>; bus-width = <24>; display-timings { native-mode = <&timing0>; timing0: timing0 { clock-frequency = <9200000>; hactive = <480>; vactive = <272>; hfront-porch = <8>; hback-porch = <4>; hsync-len = <41>; vback-porch = <2>; vfront-porch = <4>; vsync-len = <10>; hsync-active = <0>; vsync-active = <0>; de-active = <1>; pixelclk-active = <0>; }; }; }; }; &uart3 { /* BT */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; assigned-clocks = <&clk IMX8MQ_CLK_UART3_SRC>; assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; fsl,uart-has-rtscts; status = "disabled"; }; &usdhc1 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; pinctrl-1 = <&pinctrl_usdhc1_100mhz>; pinctrl-2 = <&pinctrl_usdhc1_200mhz>; bus-width = <8>; non-removable; status = "okay"; }; &usdhc2 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; bus-width = <4>; cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; //vmmc-supply = <®_usdhc2_vmmc>; status = "okay"; }; &usb3_phy0 { status = "okay"; }; &usb3_0 { status = "okay"; }; &usb_dwc3_0 { status = "okay"; dr_mode = "peripheral"; }; &usb3_phy1 { status = "okay"; }; &usb3_1 { status = "okay"; }; &usb_dwc3_1 { status = "okay"; dr_mode = "host"; }; &wdog1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_wdog>; fsl,ext-reset-output; status = "okay"; };