Commit 3263309c authored by Kenneth Chan's avatar Kenneth Chan Committed by Patrick Georgi
Browse files

mb/google/octopus/variants/dood: Disable XHCI LFPS power management

LTE module Fibocom L850-GL is lost after idle overnight, with this workaround, host will not initiate U3 wakeup at the same time with device, which will avoid the race condition.

Disable XHCI LFPS power management. If the option is set in the devicetree, the bits[7:4] in XHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated from default 9 to 0.

TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash
     the image to the device. Run following command to check if
     bits[7:4] are set 0:
     >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"
Signed-off-by: default avatarKenneth Chan <>
Change-Id: I88357f44317a5cff2e04508638eb065e5ada4c4c

Tested-by: default avatarbuild bot (Jenkins) <>
Reviewed-by: default avatarMarco Chen <>
Reviewed-by: default avatarRen Kuo <>
parent 0d0fe141
......@@ -149,4 +149,5 @@ chip soc/intel/apollolake
# Disable compliance mode
register "DisableComplianceMode" = "1"
register "disable_xhci_lfps_pm" = "0"
......@@ -8,6 +8,7 @@
#include <delay.h>
#include <gpio.h>
#include <ec/google/chromeec/ec.h>
#include <soc/intel/apollolake/chip.h>
enum {
SKU_1_LTE = 1, /* Wifi + LTE */
......@@ -61,3 +62,21 @@ void variant_smi_sleep(u8 slp_typ)
void variant_update_devtree(struct device *dev)
struct soc_intel_apollolake_config *cfg = NULL;
cfg = (struct soc_intel_apollolake_config *)dev->chip_info;
if (cfg != NULL && cfg->disable_xhci_lfps_pm) {
switch (google_chromeec_get_board_sku()) {
case SKU_1_LTE:
case SKU_3_LTE_2CAM:
cfg->disable_xhci_lfps_pm = 1;
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