Commit 75476ec3 authored by Matt DeVillier's avatar Matt DeVillier Committed by Patrick Georgi
Browse files

mb/google/cyan/*: fixup GPIOs

Commit 73b723d7 [google/cyan: Switch Touchpad and Touchscreen...]
in additon to changing the touchpad/touchscreen interrupts from
edge to level triggered, also marked them as maskable.

This was partially reverted in a86bbea0 [google/cyan: set
touchscreen GPIO to non_maskable], but did not resolve all of the
issues. Additionally, 73b723d7

 also accidentally changed the pad
interrupt select from L3 to L1 for all touchscreen GPIOs.

Clean up this mess by setting all touchpad/touchscreen GPIOs
back to maskable, and set the pad level to L3 for all touchscreen
GPIOs.

Tested on several cyan variants

Change-Id: I70e8e2d4ff317c3b9b4108ed6c5bc80e9b0bbc75
Signed-off-by: default avatarMatt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41176

Tested-by: default avatarbuild bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: default avatarAngel Pons <th3fanbus@gmail.com>
parent d6b682cf
......@@ -147,9 +147,9 @@ static const struct soc_gpio_map gpn_gpio_map[] = {
GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),
/* 17 GPIO_SUS3 */
GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA),
/* 18 GPIO_SUS7 */
GPI(trig_level_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA),
/* 18 GPIO_SUS7 */
GPI(trig_level_low, L3, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA),
/* 19 GPIO_SUS1 */
GPIO_NC, /* 20 GPIO_SUS5 */
GPIO_NC, /* 21 SEC_GPIO_SUS11 */
......
......@@ -150,7 +150,7 @@ static const struct soc_gpio_map gpn_gpio_map[] = {
GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),
/* 17 GPIO_SUS3 */
GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA),
GPI(trig_level_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA),
/* 18 GPIO_SUS7 */
GPI(trig_level_low, L3, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA),
/* 19 GPIO_SUS1 */
......
......@@ -147,7 +147,7 @@ static const struct soc_gpio_map gpn_gpio_map[] = {
GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),
/* 17 GPIO_SUS3 */
GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA),
GPI(trig_level_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA),
/* 18 GPIO_SUS7 */
GPIO_NC, /* 19 GPIO_SUS1 */
GPIO_NC, /* 20 GPIO_SUS5 */
......
......@@ -146,9 +146,9 @@ static const struct soc_gpio_map gpn_gpio_map[] = {
GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),
/* 17 GPIO_SUS3 */
GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA),
/* 18 GPIO_SUS7 */
GPI(trig_level_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA),
/* 18 GPIO_SUS7 */
GPI(trig_level_low, L3, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA),
/* 19 GPIO_SUS1 */
GPIO_NC, /* 20 GPIO_SUS5 */
GPIO_NC, /* 21 SEC_GPIO_SUS11 */
......
......@@ -149,9 +149,9 @@ static const struct soc_gpio_map gpn_gpio_map[] = {
GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),
/* 17 GPIO_SUS3 */
GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA),
/* 18 GPIO_SUS7 */
GPI(trig_level_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA),
/* 18 GPIO_SUS7 */
GPI(trig_level_low, L3, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA),
/* 19 GPIO_SUS1 */
GPIO_NC, /* 20 GPIO_SUS5 */
GPIO_NC, /* 21 SEC_GPIO_SUS11 */
......
......@@ -149,9 +149,9 @@ static const struct soc_gpio_map gpn_gpio_map[] = {
GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),
/* 17 GPIO_SUS3 */
GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA),
/* 18 GPIO_SUS7 */
GPI(trig_level_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA),
/* 18 GPIO_SUS7 */
GPI(trig_level_low, L3, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA),
/* 19 GPIO_SUS1 */
GPIO_NC, /* 20 GPIO_SUS5 */
GPIO_NC, /* 21 SEC_GPIO_SUS11 */
......
......@@ -147,9 +147,9 @@ static const struct soc_gpio_map gpn_gpio_map[] = {
GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),
/* 17 GPIO_SUS3 */
GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA),
/* 18 GPIO_SUS7 */
GPI(trig_level_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA),
/* 18 GPIO_SUS7 */
GPI(trig_level_low, L3, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA),
/* 19 GPIO_SUS1 */
GPIO_NC, /* 20 GPIO_SUS5 */
GPIO_NC, /* 21 SEC_GPIO_SUS11 */
......
......@@ -146,7 +146,7 @@ static const struct soc_gpio_map gpn_gpio_map[] = {
GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),
/* 17 GPIO_SUS3 */
GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA),
GPI(trig_level_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA),
/* 18 GPIO_SUS7 */
GPIO_NC, /* 19 GPIO_SUS1 */
GPIO_NC, /* 20 GPIO_SUS5 */
......
......@@ -149,9 +149,9 @@ static const struct soc_gpio_map gpn_gpio_map[] = {
GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),
/* 17 GPIO_SUS3 */
GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA),
/* 18 GPIO_SUS7 */
GPI(trig_level_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA),
/* 18 GPIO_SUS7 */
GPI(trig_level_low, L3, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA),
/* 19 GPIO_SUS1 */
GPIO_NC, /* 20 GPIO_SUS5 */
GPIO_NC, /* 21 SEC_GPIO_SUS11 */
......
......@@ -148,9 +148,9 @@ static const struct soc_gpio_map gpn_gpio_map[] = {
GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),
/* 17 GPIO_SUS3 */
GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA),
/* 18 GPIO_SUS7 */
GPI(trig_level_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA),
/* 18 GPIO_SUS7 */
GPI(trig_level_low, L3, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA),
/* 19 GPIO_SUS1 */
GPIO_NC, /* 20 GPIO_SUS5 */
GPIO_INPUT_NO_PULL, /* 21 SEC_GPIO_SUS11 */
......
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment