Commit 7f520c8f authored by Bob Moragues's avatar Bob Moragues Committed by Duncan Laurie
Browse files

zoombini: remove support for deprecated zoombini board



Change-Id: Iab2737940f07afb4f5a29ff50e6cb2a22027c51b
Signed-off-by: default avatarBob Moragues <moragues@chromium.org>
Reviewed-on: https://review.coreboot.org/c/30094

Reviewed-by: default avatarJulius Werner <jwerner@chromium.org>
Reviewed-by: default avatarDuncan Laurie <dlaurie@chromium.org>
Reviewed-by: default avatarNick Vaccaro <nvaccaro@google.com>
Tested-by: default avatarbuild bot (Jenkins) <no-reply@coreboot.org>
parent cb76069e
config BOARD_GOOGLE_BASEBOARD_ZOOMBINI
def_bool n
select BOARD_ROMSIZE_KB_16384
select DRIVERS_I2C_GENERIC
select DRIVERS_I2C_HID
select DRIVERS_I2C_MAX98373
select DRIVERS_SPI_ACPI
select EC_GOOGLE_CHROMEEC
select EC_GOOGLE_CHROMEEC_BOARDID
select EC_GOOGLE_CHROMEEC_LPC
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select MAINBOARD_HAS_CHROMEOS
select SOC_INTEL_CANNONLAKE
select SOC_INTEL_CANNONLAKE_MEMCFG_INIT
if BOARD_GOOGLE_BASEBOARD_ZOOMBINI
config BASEBOARD_ZOOMBINI_LAPTOP
def_bool n
select SYSTEM_TYPE_LAPTOP
config DEVICETREE
string
default "variants/meowth/devicetree.cb" if BOARD_GOOGLE_MEOWTH
default "variants/baseboard/devicetree.cb"
config DIMM_SPD_SIZE
int
default 512
config DRIVER_TPM_I2C_BUS
depends on ZOOMBINI_USE_I2C_TPM
default 0x1
config DRIVER_TPM_I2C_ADDR
depends on ZOOMBINI_USE_I2C_TPM
default 0x50
config DRIVER_TPM_SPI_BUS
depends on ZOOMBINI_USE_SPI_TPM
default 0x1
config GBB_HWID
string
depends on CHROMEOS
default "MEOWTH TEST 5868" if BOARD_GOOGLE_MEOWTH
default "ZOOMBINI TEST 5722" if BOARD_GOOGLE_ZOOMBINI
config MAINBOARD_DIR
string
default "google/zoombini"
config MAINBOARD_FAMILY
string
default "Google_Meowth" if BOARD_GOOGLE_MEOWTH
default "Google_Zoombini" if BOARD_GOOGLE_ZOOMBINI
config MAINBOARD_PART_NUMBER
string
default "Meowth" if BOARD_GOOGLE_MEOWTH
default "Zoombini" if BOARD_GOOGLE_ZOOMBINI
config MAINBOARD_VENDOR
string
default "Google"
config INCLUDE_SND_MAX98357_DA7219_NHLT
bool "Include blobs for audio with MAX98357_DA7219"
select NHLT_DMIC_4CH_16B
select NHLT_DMIC_2CH_16B
select NHLT_DA7219
select NHLT_MAX98357
config INCLUDE_SND_MAX98373_NHLT
bool "Include blobs for audio with MAX98373"
select NHLT_DMIC_4CH_16B
select NHLT_DMIC_2CH_16B
select NHLT_MAX98373
config MAX_CPUS
int
default 4
config VARIANT_DIR
string
default "meowth" if BOARD_GOOGLE_MEOWTH
default "zoombini" if BOARD_GOOGLE_ZOOMBINI
config VBOOT
select EC_GOOGLE_CHROMEEC_SWITCHES
select HAS_RECOVERY_MRC_CACHE
select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
select VBOOT_LID_SWITCH if BASEBOARD_ZOOMBINI_LAPTOP
# Select this option to enable use of cr50 I2C TPM on zoombini.
config ZOOMBINI_USE_I2C_TPM
bool
default n
select MAINBOARD_HAS_I2C_TPM_CR50
select MAINBOARD_HAS_TPM2
# Select this option to enable use of cr50 SPI TPM on zoombini.
config ZOOMBINI_USE_SPI_TPM
bool
default y
select MAINBOARD_HAS_SPI_TPM_CR50
select MAINBOARD_HAS_TPM2
config TPM_TIS_ACPI_INTERRUPT
int
default 76 # GPE0_DW2_12 (GPP_C12)
endif # BOARD_GOOGLE_BASEBOARD_ZOOMBINI
comment "Zoombini"
config BOARD_GOOGLE_ZOOMBINI
bool "-> Zoombini"
select BOARD_GOOGLE_BASEBOARD_ZOOMBINI
select BASEBOARD_ZOOMBINI_LAPTOP
config BOARD_GOOGLE_MEOWTH
bool "-> Meowth"
select BOARD_GOOGLE_BASEBOARD_ZOOMBINI
select BASEBOARD_ZOOMBINI_LAPTOP
##
## This file is part of the coreboot project.
##
## Copyright 2018 Google Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
bootblock-y += bootblock.c
bootblock-$(CONFIG_CHROMEOS) += chromeos.c
bootblock-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
verstage-$(CONFIG_CHROMEOS) += chromeos.c
romstage-$(CONFIG_CHROMEOS) += chromeos.c
romstage-y += memory.c
romstage-y += romstage.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c
ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
ramstage-y += mainboard.c
ramstage-y += ramstage.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
subdirs-y += variants/baseboard
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
subdirs-y += variants/$(VARIANT_DIR)
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
subdirs-y += variants/$(VARIANT_DIR)/spd
subdirs-y += spd
Vendor name: Google
Board name: Zoombini Cannonlake Reference Board
Category: laptop
ROM protocol: SPI
ROM socketed: n
Flashrom support: y
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2017 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <baseboard/gpio.h>
#include <baseboard/variants.h>
#include <bootblock_common.h>
#include <soc/gpio.h>
static void early_config_gpio(void)
{
const struct pad_config *early_gpio_table;
size_t num_gpios = 0;
early_gpio_table = variant_early_gpio_table(&num_gpios);
gpio_configure_pads(early_gpio_table, num_gpios);
}
void bootblock_mainboard_init(void)
{
early_config_gpio();
}
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2017 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/acpi.h>
#include <baseboard/gpio.h>
#include <boot/coreboot_tables.h>
#include <gpio.h>
#include <rules.h>
#include <soc/gpio.h>
#include <vendorcode/google/chromeos/chromeos.h>
void fill_lb_gpios(struct lb_gpios *gpios)
{
struct lb_gpio chromeos_gpios[] = {
{-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"},
{-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
{-1, ACTIVE_HIGH, 0, "power"},
{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
/* always report back 0 as temp workaround for b:74215817 */
{GPIO_EC_IN_RW, ACTIVE_HIGH, 0, "EC in RW"},
};
lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
}
int get_write_protect_state(void)
{
/* Read PCH_WP GPIO. */
return gpio_get(GPIO_PCH_WP);
}
static const struct cros_gpio cros_gpios[] = {
CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
};
void mainboard_chromeos_acpi_generate(void)
{
chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
}
FLASH@0xff000000 0x1000000 {
SI_ALL@0x0 0x300000 {
SI_DESC@0x0 0x1000
SI_ME@0x1000 0x2ff000
}
SI_BIOS@0x300000 0xd00000 {
RW_SECTION_A@0x0 0x368000 {
VBLOCK_A@0x0 0x10000
FW_MAIN_A(CBFS)@0x10000 0x357fc0
RW_FWID_A@0x367fc0 0x40
}
RW_SECTION_B@0x368000 0x368000 {
VBLOCK_B@0x0 0x10000
FW_MAIN_B(CBFS)@0x10000 0x357fc0
RW_FWID_B@0x367fc0 0x40
}
RW_MISC@0x6d0000 0x30000 {
UNIFIED_MRC_CACHE@0x0 0x20000 {
RECOVERY_MRC_CACHE@0x0 0x10000
RW_MRC_CACHE@0x10000 0x10000
}
RW_ELOG@0x20000 0x4000
RW_SHARED@0x24000 0x4000 {
SHARED_DATA@0x0 0x2000
VBLOCK_DEV@0x2000 0x2000
}
RW_VPD@0x28000 0x2000
RW_NVRAM@0x2a000 0x6000
}
SMMSTORE@0x700000 0x40000
RW_LEGACY(CBFS)@0x740000 0x1c0000
WP_RO@0x900000 0x400000 {
RO_VPD@0x0 0x4000
RO_UNUSED@0x4000 0xc000
RO_SECTION@0x10000 0x3f0000 {
FMAP@0x0 0x800
RO_FRID@0x800 0x40
RO_FRID_PAD@0x840 0x7c0
GBB@0x1000 0xef000
COREBOOT(CBFS)@0xf0000 0x300000
}
}
}
}
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright 2017 Google Inc.
* Copyright (C) 2017 Intel Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "variant/ec.h"
#include "variant/gpio.h"
#include <arch/acpi.h>
DefinitionBlock(
"dsdt.aml",
"DSDT",
0x02, // DSDT revision: ACPI v2.0 and up
OEM_ID,
ACPI_TABLE_CREATOR,
0x20110725 // OEM revision
)
{
// Some generic macros
#include <soc/intel/cannonlake/acpi/platform.asl>
// global NVS and variables
#include <soc/intel/cannonlake/acpi/globalnvs.asl>
// CPU
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)
{
#include <soc/intel/cannonlake/acpi/northbridge.asl>
#include <soc/intel/cannonlake/acpi/southbridge.asl>
}
}
#if IS_ENABLED(CONFIG_CHROMEOS)
// Chrome OS specific
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
#endif
// Chipset specific sleep states
#include <soc/intel/cannonlake/acpi/sleepstates.asl>
/* Chrome OS Embedded Controller */
Scope (\_SB.PCI0.LPCB)
{
/* ACPI code for EC SuperIO functions */
#include <ec/google/chromeec/acpi/superio.asl>
/* ACPI code for EC functions */
#include <ec/google/chromeec/acpi/ec.asl>
}
}
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2017 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/acpi.h>
#include <ec/google/chromeec/ec.h>
#include <variant/ec.h>
void mainboard_ec_init(void)
{
const struct google_chromeec_event_info info = {
.log_events = MAINBOARD_EC_LOG_EVENTS,
.sci_events = MAINBOARD_EC_SCI_EVENTS,
.s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS,
.s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS,
};
google_chromeec_events_init(&info, acpi_is_wakeup_s3());
}
/*
* This file is part of the coreboot project.
*
* Copyright 2017 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <device/device.h>
#include <ec/ec.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include <nhlt.h>
#include <arch/acpi.h>
#include <baseboard/variants.h>
static void mainboard_init(struct device *dev)
{
mainboard_ec_init();
}
static unsigned long mainboard_write_acpi_tables(struct device *device,
unsigned long current, acpi_rsdp_t *rsdp)
{
uintptr_t start_addr;
uintptr_t end_addr;
struct nhlt *nhlt;
start_addr = current;
nhlt = nhlt_init();
if (nhlt == NULL)
return start_addr;
variant_nhlt_init(nhlt);
end_addr = nhlt_soc_serialize(nhlt, start_addr);
if (end_addr != start_addr)
acpi_add_table(rsdp, (void *)start_addr);
return end_addr;
}
static void mainboard_enable(struct device *dev)
{
dev->ops->init = mainboard_init;
dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
}
struct chip_operations mainboard_ops = {
.enable_dev = mainboard_enable,
};
/*
* This file is part of the coreboot project.
*
* Copyright 2017 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <baseboard/variants.h>
#include <baseboard/gpio.h>
#include <gpio.h>
#include <soc/cnl_memcfg_init.h>
static const struct cnl_mb_cfg baseboard_lpddr4_cfg = {
.dq_map[DDR_CH0] = {
/*
* CLK0 goes to package 0 - Bytes[3:0],
* CLK1 goes to package 1 - Bytes[7:4]
*/
{ 0x0F, 0xF0 },
/*
* Cmd CAA goes to Bytes[3:0],
* Cmd CAB goes to Bytes[7:4]
*/
{ 0x0F, 0xF0 },
/* CTL (CS) goes to all bytes */
{ 0xFF, 0x00 },
},
.dq_map[DDR_CH1] = {
/*
* CLK0 goes to package 0 - Bytes[3:0],
* CLK1 goes to package 1 - Bytes[7:4]
*/
{ 0x0F, 0xF0 },
/*
* Cmd CAA goes to Bytes[3:0],
* Cmd CAB goes to Bytes[7:4]
*/
{ 0x0F, 0xF0 },
/* CTL (CS) goes to all bytes */
{ 0xFF, 0x00 },
},
/*
* The dqs_map arrays map the lpddr4 pins to the SoC pins
* for both channels.
*
* the index = pin number on lpddr4 part
* the value = pin number on SoC
*/
.dqs_map[DDR_CH0] = { 3, 1, 2, 0, 7, 5, 6, 4 },
.dqs_map[DDR_CH1] = { 3, 2, 0, 1, 7, 5, 6, 4 },
/* Baseboard uses three 100 Ohm rcomp resistors */
.rcomp_resistor = { 100, 100, 100 },
/*
* Baseboard Rcomp target values.
* Rcomp targets for baseboard should be
* { 80, 40, 40, 40, 30 }, but we need to
* nil out rcomp targets for now to avoid bug b:70896346
*/
.rcomp_targets = { 0, 0, 0, 0, 0 },
/* Baseboard is a non-interleaved design */
.dq_pins_interleaved = 0,
/* Disable Early Command Training */
.ect = 0,
};
const struct cnl_mb_cfg *__weak variant_lpddr4_config(void)
{
return &baseboard_lpddr4_cfg;
}
size_t __weak variant_memory_sku(void)
{
const gpio_t pads[] = {
[3] = GPIO_MEM_CONFIG_3, [2] = GPIO_MEM_CONFIG_2,
[1] = GPIO_MEM_CONFIG_1, [0] = GPIO_MEM_CONFIG_0,
};
return gpio_base2_value(pads, ARRAY_SIZE(pads));
}
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2017 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <baseboard/variants.h>
#include <soc/ramstage.h>
#include <variant/gpio.h>
void mainboard_silicon_init_params(FSP_S_CONFIG *params)
{
size_t num;
const struct pad_config *gpio_table;
gpio_table = variant_gpio_table(&num);
gpio_configure_pads(gpio_table, num);
}
/*
* This file is part of the coreboot project.
*
* Copyright 2017 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.