Commit ca8968db authored by Angel Pons's avatar Angel Pons Committed by Nico Huber
Browse files

nb/intel/ironlake: Drop copy-pasted finalisation steps



This was copied from Sandy Bridge and does not apply to Ironlake. These
offsets go past the MCHBAR window (MCHBAR size is 16 KiB on Ironlake).
Some of these writes would have collided with `DEFAULT_HECIBAR` if the
PCI resource had been reported as fixed. Remove the copy-pasted code.

Change-Id: I7688921ad7517cbd68a0c48262b29ecf7b4c396c
Signed-off-by: default avatarAngel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51856

Reviewed-by: default avatarPatrick Rudolph <siro@das-labor.org>
Tested-by: default avatarbuild bot (Jenkins) <no-reply@coreboot.org>
parent 7adfe804
......@@ -4,19 +4,4 @@
void intel_ironlake_finalize_smm(void)
{
MCHBAR32_OR(0x5500, 1 << 0); /* PAVP */
MCHBAR32_OR(0x5f00, 1 << 31); /* SA PM */
MCHBAR32_OR(0x6020, 1 << 0); /* UMA GFX */
MCHBAR32_OR(0x63fc, 1 << 0); /* VTDTRK */
MCHBAR32_OR(0x6800, 1 << 31);
MCHBAR32_OR(0x7000, 1 << 31);
MCHBAR32_OR(0x77fc, 1 << 0);
/* Memory Controller Lockdown */
MCHBAR8(0x50fc) = 0x8f;
/* Read+write the following */
MCHBAR32(0x6030) = MCHBAR32(0x6030);
MCHBAR32(0x6034) = MCHBAR32(0x6034);
MCHBAR32(0x6008) = MCHBAR32(0x6008);
}
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