Commit d6b682cf authored by Wim Vervoorn's avatar Wim Vervoorn Committed by Patrick Georgi
Browse files

soc/intel/skylake: Allow setting of PcieRpMaxPayload



Add setting of the MaxPayload for each root port from the device tree.

By default MaxPayload is set to 128 bytes. This change allows changing
to 256 bytes.

BUG=N/A
TEST=tested on facebook monolith

Change-Id: I61e1d619588a7084d52bbe101acd757cc7293cac
Signed-off-by: default avatarWim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41170

Tested-by: default avatarbuild bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: default avatarFrans Hendriks <fhendriks@eltan.com>
parent f5472a10
......@@ -188,6 +188,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
sizeof(params->PcieRpLtrEnable));
memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug,
sizeof(params->PcieRpHotPlug));
for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++)
params->PcieRpMaxPayload[i] = config->PcieRpMaxPayload[i];
/*
* PcieRpClkSrcNumber UPD is set to clock source number(0-6) for
......
......@@ -284,6 +284,12 @@ struct soc_intel_skylake_config {
/* Enable/Disable HotPlug support for Root Port */
u8 PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS];
/* PCIE RP Max Payload, Max Payload Size supported */
enum {
RpMaxPayload_128,
RpMaxPayload_256,
} PcieRpMaxPayload[CONFIG_MAX_ROOT_PORTS];
/* USB related */
struct usb2_port_config usb2_ports[16];
struct usb3_port_config usb3_ports[10];
......
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