Commit efe27cf3 authored by Furquan Shaikh's avatar Furquan Shaikh
Browse files

soc/amd/common/block/lpc: Add config options for eSPI



eSPI on Picasso is configured using the LPC bridge configuration
registers. This change enables config options to allow SoC to select
if it supports eSPI (SOC_AMD_COMMON_BLOCK_HAS_ESPI) and mainboard to
select if it wants to use eSPI instead of LPC for talking to legacy
devices and embedded controllers (SOC_AMD_COMMON_BLOCK_USE_ESPI).

BUG=b:154445472

Change-Id: I15e9eb25706e09393c019eea4d61b66f17490be6
Signed-off-by: default avatarFurquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41069

Reviewed-by: default avatarRaul Rangel <rrangel@chromium.org>
Reviewed-by: default avatarAaron Durbin <adurbin@chromium.org>
Tested-by: default avatarbuild bot (Jenkins) <no-reply@coreboot.org>
parent 235a7512
......@@ -9,3 +9,18 @@ config PROVIDES_ROM_SHARING
default n
help
Select this option if the LPC bridge supports ROM sharing.
config SOC_AMD_COMMON_BLOCK_HAS_ESPI
bool
default n
help
Select this option if platform supports eSPI using D14F3 configuration
registers.
config SOC_AMD_COMMON_BLOCK_USE_ESPI
bool
depends on SOC_AMD_COMMON_BLOCK_HAS_ESPI
default n
help
Select this option if mainboard uses eSPI instead of LPC (if supported
by platform).
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