Commit fc0e17df authored by Matt Devillier's avatar Matt Devillier
Browse files

mb/purism/librem_cnl: Adjust in preparation for new variants



sync librem_cnl with coreboot upstream in preparation for addition
of new Librem Mini v2 board

Change-Id: Ic19bf6083557cedc96679a3f77187d75fecc4f0e
Signed-off-by: Matt Devillier's avatarMatt DeVillier <matt.devillier@puri.sm>
parent 2e262e84
......@@ -126,6 +126,10 @@ The boards in this section are not real mainboards, but emulators.
- [PQ7-M107](portwell/pq7-m107.md)
## Purism
- [Librem Mini](purism/librem_mini.md)
## Protectli
- [FW2B / FW4B](protectli/fw2b_fw4b.md)
......
# Purism Librem Mini
This page describes how to run coreboot on the [Purism Librem Mini].
```eval_rst
+------------------+--------------------------------------------------+
| CPU | Intel Core i7-8565U/8665U |
+------------------+--------------------------------------------------+
| PCH | Whiskey Lake / Cannon Point LP |
+------------------+--------------------------------------------------+
| Super I/O, EC | ITE IT8528E |
+------------------+--------------------------------------------------+
| Coprocessor | Intel Management Engine (CSME 12.x) |
+------------------+--------------------------------------------------+
```
![](librem_mini.jpg)
![](librem_mini_flash.jpg)
## Required proprietary blobs
To build a minimal working coreboot image some blobs are required (assuming
only the BIOS region is being modified).
```eval_rst
+-----------------+---------------------------------+---------------------+
| Binary file | Apply | Required / Optional |
+=================+=================================+=====================+
| FSP-M, FSP-S | Intel Firmware Support Package | Required |
+-----------------+---------------------------------+---------------------+
| microcode | CPU microcode | Required |
+-----------------+---------------------------------+---------------------+
| vgabios | VGA Option ROM | Optional |
+-----------------+---------------------------------+---------------------+
```
FSP-M and FSP-S are obtained after splitting the Coffee Lake FSP binary (done
automatically by the coreboot build system and included into the image) from
the `3rdparty/fsp` submodule.
Microcode updates are automatically included into the coreboot image by the build
system from the `3rdparty/intel-microcode` submodule. Official Purism release
images may include newer microcode, which is instead pulled from Purism's
[purism-blobs] repository.
VGA Option ROM is not required to boot, but if one needs graphics in pre-OS
stage, it should be included (if not using FSP/GOP display init). It can
be extracted via cbfstool from the existing board firmware or pulled from
the [purism-blobs] repository.
## Intel Management Engine
The Librem Mini uses version 12.x of the Intel Management Engine (ME) /
Converged Security Engine (CSE). The ME/CSE is disabled using the High
Assurance Platform (HAP) bit, which puts the ME into a disabled state
after platform bring-up (BUP) and disables all PCI/HECI interfaces.
This can be verified via the coreboot cbmem utility:
`sudo ./cbmem -1 | grep 'ME:'`
provided coreboot has been modified to output the ME status even when
the PCI device is not visible/active (as it is in Purism's release builds).
## Flashing coreboot
### Internal programming
The main SPI flash can be accessed using [flashrom]. The first version
supporting the chipset is flashrom v1.2. Firmware an be easily flashed
with internal programmer (either BIOS region or full image).
### External programming
The system has an internal flash chip which is a 8 MiB soldered SOIC-8 chip,
and has a diode attached to the VCC line for in-system programming.
This chip is located on the bottom side of the board under the CPU heatsink,
in line with the front USB 2.0 ports.
One has to remove all screws (in order):
* 2 top cover screws
* 4 screws securing the mainboard to the chassis
* 4 screws securing the heatsink/fan assembly to the mainboard (under the SODIMMs)
The m.2 SSD will need to be removed if the Wi-Fi antenna are connected to
an internal Wi-Fi/BT module. Use a SOIC-8 chip clip to program the chip.
Specifically, it's a Winbond W25Q128JV (3.3V) - [datasheet][W25Q128JV].
The EC firmware is stored on a separate SOIC-8 chip (a Winbond W25Q80DV),
but is not protected by a diode and therefore cannot be read/written to without
desoldering it from the mainboard.
## Known issues
* SeaBIOS can be finicky with detecting USB devices
* Mode switching with VGA option ROM display init can be slow and sometimes hangs
* Some SATA devices on the 2.5" interface can have issues operating at 6 Gbps,
despite the HSIO PHY settings being set optimally via experimentation. These devices
may show errors in dmesg and drop down to 3 Gbps, but should not fail to boot.
The same issue is present on the AMI vendor firmware.
## Working
* External displays via HDMI/DisplayPort with VGA option ROM or FSP/GOP init
(no libgfxinit support yet)
* SeaBIOS (1.13.x), Tianocore (CorebootPayloadpkg), Heads (Purism downstream) payloads
* Ethernet, m.2 2230 Wi-Fi
* System firmware updates via flashrom
* PCIe NVMe
* m.2 and SATA III
* Audio via front 3.5mm jack, HDMI, and DisplayPort
* SMBus (reading SPD from DIMMs)
* Initialization with CFL FSP 2.0
* S3 Suspend/Resume
* Booting PureOS 9.x, Debian 10.x, Qubes 4.0.3, Linux Mint 19.3, Windows 10 2004
## Not working / untested
* ITE IT8528E Super IO functions
[Purism Librem Mini]: https://puri.sm/products/librem-mini/
[purism-blobs]: https://source.puri.sm/coreboot/purism-blobs
[W25Q128JV]: https://www.winbond.com/resource-files/w25q128jv%20revf%2003272018%20plus.pdf
[flashrom]: https://flashrom.org/Flashrom
......@@ -2,13 +2,13 @@ config BOARD_PURISM_BASEBOARD_LIBREM_CNL
def_bool n
select BOARD_ROMSIZE_KB_16384
select DRIVERS_GENERIC_CBFS_SERIAL
select DRIVERS_USB_ACPI
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select INTEL_GMA_HAVE_VBT
select NO_UART_ON_SUPERIO
select SOC_INTEL_COMMON_BLOCK_HDA
select SOC_INTEL_COMMON_BLOCK_HDA_VERB
select SOC_INTEL_WHISKEYLAKE
select SPD_READ_BY_WORD
select USE_LEGACY_8254_TIMER
......@@ -30,9 +30,13 @@ config VARIANT_DIR
string
default "librem_mini" if BOARD_PURISM_LIBREM_MINI
config DEVICETREE
string
default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"
config CBFS_SIZE
hex
default 0x800000
default 0x800000 if BOARD_PURISM_LIBREM_MINI
config MAX_CPUS
int
......@@ -48,7 +52,7 @@ config DIMM_SPD_SIZE
config VGA_BIOS_ID
string
default "8086,3ea0"
default "8086,3ea0" if BOARD_PURISM_LIBREM_MINI
config PXE_ROM_ID
string
......
config BOARD_PURISM_LIBREM_MINI
bool "Librem Mini"
select BOARD_PURISM_BASEBOARD_LIBREM_CNL
select SOC_INTEL_WHISKEYLAKE
##
##
##
## SPDX-License-Identifier: GPL-2.0-only
ramstage-y += variants/$(VARIANT_DIR)/gpio.c
......
/* SPDX-License-Identifier: GPL-2.0-only */
Scope (\_SB.PCI0.LPCB) {
Scope (\_SB.PCI0.LPCB)
{
Device (AC)
{
Name (_HID, "ACPI0003")
......
Vendor name: Purism
Board name: librem_cnl
Category: desktop
Board name: Librem Cannonlake baseboard
Category: misc
Release year: 2020
ROM package: SOIC-8
ROM protocol: SPI
......
......@@ -54,6 +54,6 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
/* Enable and set SATA HSIO adjustments for ports 0 and 2 */
mem_cfg->PchSataHsioRxGen3EqBoostMagEnable[0] = 1;
mem_cfg->PchSataHsioRxGen3EqBoostMagEnable[2] = 1;
mem_cfg->PchSataHsioRxGen3EqBoostMag[0] = 1;
mem_cfg->PchSataHsioRxGen3EqBoostMag[0] = 2;
mem_cfg->PchSataHsioRxGen3EqBoostMag[2] = 1;
}
Vendor name: Purism
Board name: Librem Mini
Category: desktop
Release year: 2020
ROM package: SOIC-8
ROM protocol: SPI
ROM socketed: n
Flashrom support: y
......@@ -4,23 +4,10 @@ chip soc/intel/cannonlake
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
}"
# Send an extra VR mailbox command for the PS4 exit issue
register "SendVrMbxCmd" = "2"
# ACPI (soc/intel/cannonlake/acpi.c)
# Disable s0ix
register "s0ix_enable" = "0"
# PM Timer Enabled
register "PmTimerDisabled" = "0"
# Disable DPTF
register "dptf_enable" = "0"
# CPU (soc/intel/cannonlake/cpu.c)
# Power limit
register "tdp_pl1_override" = "15"
register "tdp_pl2_override" = "25"
register "tdp_pl1_override" = "25"
register "tdp_pl2_override" = "51"
# Enable "Intel Speed Shift Technology"
register "speed_shift_enable" = "1"
......@@ -29,114 +16,12 @@ chip soc/intel/cannonlake
register "eist_enable" = "1"
# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
register "SaGv" = "SaGv_Enabled"
register "SaGv" = "SaGv_FixedHigh"
# FSP Silicon (soc/intel/cannonlake/fsp_params.c)
# Serial I/O
register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoDisabled,
[PchSerialIoIndexI2C1] = PchSerialIoDisabled,
[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
[PchSerialIoIndexSPI0] = PchSerialIoDisabled,
[PchSerialIoIndexSPI1] = PchSerialIoDisabled,
[PchSerialIoIndexSPI2] = PchSerialIoDisabled,
[PchSerialIoIndexUART0] = PchSerialIoDisabled,
[PchSerialIoIndexUART1] = PchSerialIoDisabled,
[PchSerialIoIndexUART2] = PchSerialIoDisabled,
}"
# SATA
register "SataMode" = "Sata_AHCI"
register "SataSalpSupport" = "0"
register "SataPortsEnable[0]" = "1" # 2.5"
register "SataPortsEnable[2]" = "1" # m.2
register "SataPortsDevSlp[0]" = "0"
register "SataPortsDevSlp[2]" = "0"
# Audio
register "PchHdaDspEnable" = "0"
register "PchHdaAudioLinkHda" = "1"
register "PchHdaAudioLinkDmic0" = "0"
register "PchHdaAudioLinkDmic1" = "0"
register "PchHdaAudioLinkSsp0" = "0"
register "PchHdaAudioLinkSsp1" = "0"
register "PchHdaAudioLinkSsp2" = "0"
register "PchHdaAudioLinkSndw1" = "0"
register "PchHdaAudioLinkSndw2" = "0"
register "PchHdaAudioLinkSndw3" = "0"
register "PchHdaAudioLinkSndw4" = "0"
# USB
register "SsicPortEnable" = "0"
# USB2
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front left upper
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front left lower
register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A rear upper
register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front right lower
register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front right upper
register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC3)" # Type-C rear
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # m.2-2230/Bluetooth
register "usb2_ports[7]" = "USB2_PORT_EMPTY" # NC
register "usb2_ports[8]" = "USB2_PORT_EMPTY" # NC
register "usb2_ports[9]" = "USB2_PORT_MID(OC2)" # Type-A rear lower
register "usb2_ports[10]" = "USB2_PORT_EMPTY" # NC
register "usb2_ports[11]" = "USB2_PORT_EMPTY" # NC
register "usb2_ports[12]" = "USB2_PORT_EMPTY" # NC
register "usb2_ports[13]" = "USB2_PORT_EMPTY" # NC
register "usb2_ports[14]" = "USB2_PORT_EMPTY" # NC
register "usb2_ports[15]" = "USB2_PORT_EMPTY" # NC
# USB3
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A front left upper
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A front left lower
register "usb3_ports[2]" = "USB3_PORT_EMPTY" # NC
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-C rear
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" # Type-A rear lower
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC2)" # Type-A rear upper
register "usb3_ports[6]" = "USB3_PORT_EMPTY" # NC
register "usb3_ports[7]" = "USB3_PORT_EMPTY" # NC
register "usb3_ports[8]" = "USB3_PORT_EMPTY" # NC
register "usb3_ports[9]" = "USB3_PORT_EMPTY" # NC
# All SRCCLKREQ pins mapped directly
register "PcieClkSrcClkReq[0]" = "0"
register "PcieClkSrcClkReq[1]" = "1"
register "PcieClkSrcClkReq[2]" = "2"
register "PcieClkSrcClkReq[3]" = "3"
register "PcieClkSrcClkReq[4]" = "4"
register "PcieClkSrcClkReq[5]" = "5"
# Set all SRCCLKREQ pins as free-use
register "PcieClkSrcUsage[0]" = "0x80"
register "PcieClkSrcUsage[1]" = "0x80"
register "PcieClkSrcUsage[2]" = "0x80"
register "PcieClkSrcUsage[3]" = "0x80"
register "PcieClkSrcUsage[4]" = "0x80"
register "PcieClkSrcUsage[5]" = "0x80"
# PCI Express Root Port #8 x1, Clock 2 (WLAN)
register "PcieRpEnable[7]" = "1"
register "PcieRpLtrEnable[7]" = "1"
# PCI Express Root Port #10 x1, Clock 3 (LAN)
register "PcieRpEnable[9]" = "1"
register "PcieRpLtrEnable[9]" = "0"
# PCI Express Root port #13 x4, Clock 1 (NVMe)
register "PcieRpEnable[12]" = "1"
register "PcieRpLtrEnable[12]" = "1"
# Misc
register "Device4Enable" = "1"
# HECI must be enabled w/HAP disable else S3 issues
register "HeciEnabled" = "1"
register "Heci3Enabled" = "0"
register "AcousticNoiseMitigation" = "1"
register "satapwroptimize" = "1"
# Power
register "PchPmSlpS3MinAssert" = "3" # 50ms
......@@ -150,10 +35,6 @@ chip soc/intel/cannonlake
# Serial IRQ Mode
register "serirq_mode" = "SERIRQ_CONTINUOUS"
# PMC (soc/intel/cannonlake/pmc.c)
# Disable deep Sx states
register "deep_sx_config" = "0"
# PM Util (soc/intel/cannonlake/pmutil.c)
# GPE configuration
# Note that GPE events called out in ASL code rely on this
......@@ -172,22 +53,149 @@ chip soc/intel/cannonlake
device domain 0 on
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device
device pci 04.0 on end # SA Thermal device
device pci 04.0 on # SA Thermal device
register "Device4Enable" = "1"
end
device pci 12.0 on end # Thermal Subsystem
device pci 13.0 off end # Integrated Sensor Hub
device pci 14.0 on end # USB xHCI
device pci 14.0 on # USB xHCI
chip drivers/usb/acpi
device usb 0.0 on
chip drivers/usb/acpi
register "desc" = ""USB2 Type-A Front Left Upper""
register "type" = "UPC_TYPE_A"
register "group" = "ACPI_PLD_GROUP(0, 0)"
device usb 2.0 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-A Front Left Lower""
register "type" = "UPC_TYPE_A"
register "group" = "ACPI_PLD_GROUP(0, 1)"
device usb 2.1 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-A Rear Upper""
register "type" = "UPC_TYPE_A"
register "group" = "ACPI_PLD_GROUP(1, 0)"
device usb 2.2 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-A Front Right Lower""
register "type" = "UPC_TYPE_A"
register "group" = "ACPI_PLD_GROUP(0, 2)"
device usb 2.3 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-A Front Right Upper""
register "type" = "UPC_TYPE_A"
register "group" = "ACPI_PLD_GROUP(0, 3)"
device usb 2.4 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-C Port Rear""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "group" = "ACPI_PLD_GROUP(1, 2)"
device usb 2.5 on end
end
chip drivers/usb/acpi
device usb 2.6 off end
end
chip drivers/usb/acpi
device usb 2.7 off end
end
chip drivers/usb/acpi
device usb 2.8 off end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-A Rear Lower""
register "type" = "UPC_TYPE_A"
register "group" = "ACPI_PLD_GROUP(1, 1)"
device usb 2.9 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-A Front Left Upper""
register "type" = "UPC_TYPE_USB3_A"
register "group" = "ACPI_PLD_GROUP(0, 0)"
device usb 3.0 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-A Front Left Lower""
register "type" = "UPC_TYPE_USB3_A"
register "group" = "ACPI_PLD_GROUP(0, 1)"
device usb 3.1 on end
end
chip drivers/usb/acpi
device usb 3.2 off end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-C Rear""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "group" = "ACPI_PLD_GROUP(1, 2)"
device usb 3.3 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-A Rear Lower""
register "type" = "UPC_TYPE_USB3_A"
register "group" = "ACPI_PLD_GROUP(1, 1)"
device usb 3.4 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-A Rear Upper""
register "type" = "UPC_TYPE_USB3_A"
register "group" = "ACPI_PLD_GROUP(1, 0)"
device usb 3.5 on end
end
end
end
register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-A front left upper
register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-A front left lower
register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A rear upper
register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" # Type-A front right lower
register "usb2_ports[4]" = "USB2_PORT_MID(OC1)" # Type-A front right upper
register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC3)" # Type-C rear
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # m.2-2230/Bluetooth
register "usb2_ports[7]" = "USB2_PORT_EMPTY" # NC
register "usb2_ports[8]" = "USB2_PORT_EMPTY" # NC
register "usb2_ports[9]" = "USB2_PORT_MID(OC2)" # Type-A rear lower
register "usb2_ports[10]" = "USB2_PORT_EMPTY" # NC
register "usb2_ports[11]" = "USB2_PORT_EMPTY" # NC
register "usb2_ports[12]" = "USB2_PORT_EMPTY" # NC
register "usb2_ports[13]" = "USB2_PORT_EMPTY" # NC
register "usb2_ports[14]" = "USB2_PORT_EMPTY" # NC
register "usb2_ports[15]" = "USB2_PORT_EMPTY" # NC
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-A front left upper
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Type-A front left lower
register "usb3_ports[2]" = "USB3_PORT_EMPTY" # NC
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-C rear
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" # Type-A rear lower
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC2)" # Type-A rear upper
register "usb3_ports[6]" = "USB3_PORT_EMPTY" # NC
register "usb3_ports[7]" = "USB3_PORT_EMPTY" # NC
register "usb3_ports[8]" = "USB3_PORT_EMPTY" # NC
register "usb3_ports[9]" = "USB3_PORT_EMPTY" # NC
end
device pci 14.1 off end # USB xDCI (OTG)
device pci 15.0 off end # I2C #0
device pci 15.1 off end # I2C #1
device pci 15.2 off end # I2C #2
device pci 15.3 off end # I2C #3
device pci 16.0 off end # Management Engine Interface 1
device pci 16.0 off # Management Engine Interface 1
# HECI must be enabled w/HAP disable else S3 issues
register "HeciEnabled" = "1"
end
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT Redirection
device pci 16.4 off end # Management Engine Interface 3
device pci 16.4 off # Management Engine Interface 3
register "Heci3Enabled" = "0"
end
device pci 16.5 off end # Management Engine Interface 4
device pci 17.0 on end # SATA
device pci 17.0 on # SATA
register "SataMode" = "Sata_AHCI"
register "SataPortsEnable[0]" = "1" # 2.5"
register "SataPortsEnable[2]" = "1" # m.2
register "satapwroptimize" = "1"
end
device pci 19.0 off end # I2C #4
device pci 19.1 off end # I2C #5
device pci 19.2 off end # UART #2
......@@ -199,12 +207,31 @@ chip soc/intel/cannonlake
device pci 1c.4 off end # PCI Express Port 5
device pci 1c.5 off end # PCI Express Port 6
device pci 1c.6 off end # PCI Express Port 7
device pci 1c.7 on end # PCI Express Port 8 (WLAN)
device pci 1d.0 on end # PCI Express Port 9
device pci 1d.1 on end # PCI Express Port 10 (LAN)
device pci 1c.7 on # PCI Express Port 8
device pci 00.0 on end # x1 M.2/E 2230 (WLAN)
register "PcieRpEnable[7]" = "1"
register "PcieRpLtrEnable[7]" = "1"
# ClkSrcUsage must be set to free-run since SRCCLKREQ2 is NC
register "PcieClkSrcUsage[2]" = "0x80"
smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230" "SlotDataBusWidth1X"
end
device pci 1d.0 off end # PCI Express Port 9
device pci 1d.1 on # PCI Express Port 10
device pci 00.0 on end # x1 (LAN)
register "PcieRpEnable[9]" = "1"
register "PcieClkSrcUsage[3]" = "9"
register "PcieClkSrcClkReq[3]" = "3"
end
device pci 1d.2 off end # PCI Express Port 11
device pci 1d.3 off end # PCI Express Port 12
device pci 1d.4 on end # PCI Express Port 13 (NVMe)
device pci 1d.4 on # PCI Express Port 13
device pci 00.0 on end # x4 M.2/M 2280 (NVMe)
register "PcieRpEnable[12]" = "1"
register "PcieRpLtrEnable[12]" = "1"
register "PcieClkSrcUsage[1]" = "12"
register "PcieClkSrcClkReq[1]" = "1"
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"
end
device pci 1d.5 off end # PCI Express Port 14
device pci 1d.6 off end # PCI Express Port 15
device pci 1d.7 off end # PCI Express Port 16
......@@ -215,7 +242,9 @@ chip soc/intel/cannonlake
device pci 1f.0 on end # LPC Bridge
device pci 1f.1 off end # P2SB
device pci 1f.2 off end # Power Management Controller
device pci 1f.3 on end # Intel HDA
device pci 1f.3 on # Intel HDA
register "PchHdaAudioLinkHda" = "1"
end
device pci 1f.4 on end # SMBus
device pci 1f.5 on end # PCH SPI
device pci 1f.6 off end # GbE
......
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