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Change-Id: I5e35580a5960705fe14fc27d9f5cf0f6f660f99d
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>

Change-Id: I3105cd010f8e34ab6f4a1e9d0f9f73f129ddde17
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>

Adjust blob paths in configs for Mini v1 due to submodule update.

Change-Id: I4bb079a7ee713928aefe44471c8bc8d27d128bd6
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>

- Update VGA BIOS for Mini to 10.0.1026 (headless)
- Update CPU microcode for SKL, KBL, WHL
- Add blobs for Librem Mini v2
- Update IFD/ME blobs for Librem Mini:
  allow for larger BIOS region/larger CBFS
- Combine WHL and CML blobs under CNL

Change-Id: I0590186060263e61babb4e8c12578fa286d54cdc
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>

Add Kconfig entries, and update existing documentation to
accomodate both v1/v2 versions of the board.

Change-Id: I856bb914941211cfbec4fed871ba2a5a038e23c3
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>

sync librem_cnl with coreboot upstream in preparation for addition
of new Librem Mini v2 board

Change-Id: Ic19bf6083557cedc96679a3f77187d75fecc4f0e
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>

Since Whiskeylake SoC code is actually a subset of soc/intel/cannonlake,
rename the baseboard so that boards using other 'cannonlake family' SoCs
(e.g., Cometlake) can be added with minimal confusion.

Rename the mainboard dir and baseboard name, and adjust any references
to them.

Change-Id: I2af7977f1622070eb8bf8449bc8306f9d75b9851
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47050Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

When asked to place cbmem_top(), FSP does not seem to care about
alignment. It can return an address that is MTRR poison, which will
exhaust all variable MTRRs when trying to set up caching for CBMEM.
This will make memory-mapped flash and TSEG caching fail as well.

Safeguard against this by aligning the region to cache to half of its
size, and move it upwards to compensate. It is assumed that caching
memory above the provided bootloader TOLUM address is inconsequential.

TEST=Boot Purism Librem Mini WHL, observe no MTRR exhaustion error
     messages in console. The boot process also feels more fluid.

Change-Id: Ic64fd6d3d9e8ab4c78d68b910a476f9c4eb2d353
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45930Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

Drop Librem Mini heads config since board upstreamed now

Change-Id: I1271d868b1631e2b6cf2c56ee78156a4dc8818a3
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>

Seems to not hang with update VBIOS, so enable using 1280x1024 splash

Change-Id: I66b350e1a7b6f9338a89a6e9a77034be6b6a7c20
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>

Update VGA BIOS for Librem Mini

Change-Id: I6f67786d1b7e8a94b3f7af579c2db0d4a5c0a0b7
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>

Some Librem Minis exhibit issues with 6Gbps SATA operation on certain
SSDs, setting the Receiver Equalization Boost Magnitude adjustment
resolves this, so limiting SATA speeds to 3Gbps is no longer needed.

Test: build/boot Librem Mini with Crucial SATA SSD, observe no issues
booting, no ATA-related errors in dmesg on PureOS 10 / kernel 5.8.7

Change-Id: I8b3cbcff7f181bcab35d71e859033578c822bb20
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>

Some Librems have issues with 6Gbps SATA operation on certain
SSDs, setting the Receiver Equalization Boost Magnitude adjustment
resolves this.

Test: build/boot Librem 15v3 with Crucial SATA SSD, observe no issues
booting, no ATA-related errors in dmesg on PureOS 10 / kernel 5.8.7

Change-Id: I078deeff7fc54694393b5b16c41c5d622b332781
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>

Update toolchain to commit 48da77692ad5325c702fb07445f0e5c6dfc10f16
to fix compilation issues with coreinfo

Change-Id: I50d65aa7f32e29f00880a5d36943b8e5c44964bd
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>

After `make clean` a new build should not be based on stale artifacts.
Hence we have to remove them.

Change-Id: I18292c674986078d991668124193b6aa31234d47
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44179Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

Add patch to fix usb devices which don't use the primary
interface descriptor. Fixes UHK 60, among others

Change-Id: Ice52cc9b7151f056569ae051cfcbab662aa3c2d1
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>

Change-Id: Id3e1a8cfbe4dbd62e21bed6a3bfa77647a38fb14
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>

Rename so all boards use librem_<boardname>.
Update version to 4.12-Purism-2

Change-Id: I6c114d5df8592027508aa908a70e15b548e1c720
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>

This effectively reverts:
5086ccef [mb/purism/librem_skl: Fix CLKREQ for 15v3 NVMe]

Some Librem 15v3/v4 boards are showing issues with NVMe detection or
booting via SeaBIOS, so revert this until a proper fix can be found.

Test: build / successfully boot Librem 15v4 with problematic NVMe drive.

Change-Id: I0659f77bbe693f3d3b192a28ff3ef013658930cc
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>

unconditionally selecting GFX_GMA_IGNORE_PRESENCE_STRAPS creates a
hard dependency on MAINBOARD_USE_LIBGFXINIT, preventing a user from
using an alternative (or no) display init, so guard it appropriately.

Test: build Librem 13v4 with FSP, VGA, and no display init.

Change-Id: Ibdfe0b2bf26a9a49fb5cb669329690894de71dbd
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>

Librem Mini still uses a VBIOS for display init, needs a differently-
sized bootsplash image than other Librems using libgfxinit.

Add an extry for the NVMe drive on the LM to the default bootorder.

Add an 8s SeaBIOS boot menu delay for the LM to give the display enough
time to init, show the boot splash, and for the user to opt to show the menu.

UEFI and HEADS configs are for testing/convenience, not distribution.
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Change-Id: I30462cf05b365ee224ca44d5f90ae798f185473a

Add new librem_whl baseboard and Librem Mini variant
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Change-Id: I36af42766f85eb17f86f6ec9b48b87125fb911e6

Pull in IFD with HAP bit set for Librem Mini.
Pull in ucode support for 806ec CPUID

Change-Id: Id9c47801376f0bfdb61f33b0041e28eceb317471
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>

Print the ME status even if the CSE device is disabled, so
we know which disabled state it's in.

Change-Id: I939333199aa699039fec727beb094e4eb2ad7149
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>

Change-Id: I1ea470ce710a3d32cc0e5a3be591dff343be1932
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>

Checking the HECI device status before printing means it will skip
printing for devices with the ME disabled, leaving the user no easy
way to verify the ME is properly disabled. Remove the check.

Test: build/boot Librem 13v4, verify ME status printed as expected
on device with disabled/neutered ME.
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Change-Id: Iaa4f4a369d878a52136c3479027443ea4e731a36

Some Librem 13v4's don't have the presence straps connected,
leading libgfxinit to fail to init the internal display.
Select GFX_GMA_IGNORE_PRESENCE_STRAPS since all SKL/KBL Librems
have an internal display so there's no adverse effect.
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Change-Id: Ib9d281b7d495c4f9a5c6fc5fdb8042b0fcbda745
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41417Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

A handful of boards do not properly implement the presence straps,
leading libgfxinit to fail to detect an attached display. Add an
override, defaulting to N, which can be set for affected boards.

Add a section to the documentation detailing the option and its usage.
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Change-Id: I43c61d67147878887658b23d90fb1c0b91e7a2af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41416Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

Update libgfxinit submodule pointer to pull in handling for
presence straps bypass and some minor cleanup.
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Change-Id: Id4a903383f32f352aa3595bd72bc5f6f0777171c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41515Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

Patch SeaBIOS to not start in console mode if a bootsplash
image is to be displayed, eliminating the flicker from
starting in conole mode then immediately switchint to the bootslpash.

Adjust application of patch file so as to make for a reproducible build.
The committer name, email and date needs to match the author's
otherwise on every build, seabios will have a different commit
hash for HEAD, which can be problematic for reproducable builds
but also could confuse people if every time they type 'make', they
get a different hash of their rom

Change-Id: I493c90e73722aa8046262fc0a97fcdeab12982a4
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>

Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Change-Id: I449f4c6f4abcf3d8dcea12f62ca19215098dd29d

Required since we don't have our own fork of the
3rdparty submodules repositories (and have no need to)
in order to build without referencing the upstream repo
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Change-Id: Id51a66938dd749fd884cdf3c4df40402854fce6f

Fill in some blanks for 4.12, mark it done, add template for 4.13.
Also update the list of vboot supported boards.

Change-Id: Id6b663f13367eb40e66af30aadd33991c8dd635c
Signed-off-by: Patrick Georgi <patrick@georgi.software>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41259Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

We only write to the IOSAV LFSR registers twice, but we do so between
the writes to the other four IOSAV per-subsequence registers. Since we
know that the IOSAV is sleeping when we program the subsequences, we
might as well do the two oddball LFSR register writes after we have
programmed the always-written-to group of four registers. That way,
subsequent changes can reproducibly replace the four writes with a
single macro.

Tested on Asus P8Z77-V LX2, still boots.

Change-Id: If7bb14a9862a53a3eba565d17401347dcc9ffbe9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40973Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Reorder the order of the operands in three register writes, so that
replacing them with macros in a follow-up does not change the binary.

Tested on Asus P8Z77-V LX2, still boots.

Change-Id: I44aee9c0f49770586de322ee7f44c3609dbadd0b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40972Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

This patch implements the pin changes needed for Trogdor rev1.
Unfortunately, coreboot has to get the EC and TPM SPI busses compiled
into Kconfig, so we cannot really build a single image that runs on both
revisions. Introduce a Kconfig to handle this instead.

Change-Id: I2e48dc4565682c12089b6cf92c29f4cef4d61bb8
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38773Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Add support to configure the Silver and L3 PLLs and switch the APSS
GFMUX to use the PLL to speed up the boot cores.

Tested: CPU speed frequency validated for speed bump

Change-Id: Iafd3b618fb72e0e8cc8dd297e4a3e16b83550883
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39234Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>

Update memory regions, etc.

Change-Id: If852fe4465fb431809570be6cdccff3ad9d9f4f0
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39362Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Change-Id: I63f35c94bc6c60934ace5fe0fd9176443059b354
Signed-off-by: Ashwin Kumar <ashk@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36518Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Required for TPM IRQ.

Change-Id: I8198213cf2808be5291620892185b1e534263e3f
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38714Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>