- 29 Mar, 2021 6 commits
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Matt Devillier authored
Change-Id: I1ea470ce710a3d32cc0e5a3be591dff343be1932 Signed-off-by:
Matt DeVillier <matt.devillier@puri.sm>
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Matt Devillier authored
Checking the CSE device status before printing means it will skip printing for devices with the ME disabled, leaving the user no easy way to verify the ME is properly disabled. Remove the check. Test: build/boot Librem Mini, verify ME status printed as expected on device with disabled/neutered ME. Change-Id: I939333199aa699039fec727beb094e4eb2ad7149 Signed-off-by:
Matt DeVillier <matt.devillier@puri.sm>
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Matt Devillier authored
Checking the CSE device status before printing means it will skip printing for devices with the ME disabled, leaving the user no easy way to verify the ME is properly disabled. Remove the check. Test: build/boot Librem 13v4, verify ME status printed as expected on device with disabled/neutered ME. Signed-off-by:
Matt DeVillier <matt.devillier@puri.sm> Change-Id: Iaa4f4a369d878a52136c3479027443ea4e731a36
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Matt Devillier authored
Patch SeaBIOS to not start in console mode if a bootsplash image is to be displayed, eliminating the flicker from starting in conole mode then immediately switchint to the bootslpash. Adjust application of patch file so as to make for a reproducible build. The committer name, email and date needs to match the author's otherwise on every build, seabios will have a different commit hash for HEAD, which can be problematic for reproducable builds but also could confuse people if every time they type 'make', they get a different hash of their rom Change-Id: I493c90e73722aa8046262fc0a97fcdeab12982a4 Signed-off-by:
Matt DeVillier <matt.devillier@puri.sm>
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Matt Devillier authored
Signed-off-by:
Matt DeVillier <matt.devillier@puri.sm> Change-Id: I449f4c6f4abcf3d8dcea12f62ca19215098dd29d
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Matt Devillier authored
Required since we don't have our own fork of the 3rdparty submodules repositories (and have no need to) in order to build without referencing the upstream repo Signed-off-by:
Matt DeVillier <matt.devillier@puri.sm> Change-Id: Id51a66938dd749fd884cdf3c4df40402854fce6f
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- 28 Mar, 2021 34 commits
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Angel Pons authored
Reference code does a 32-bit write, and the values don't fit in 16 bits. Change-Id: I1195c0637b5c215a45328ebae312cf620cd4c950 Signed-off-by:
Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51860 Reviewed-by:
Patrick Rudolph <siro@das-labor.org> Tested-by:
build bot (Jenkins) <no-reply@coreboot.org>
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Angel Pons authored
Reference code uses the `0x06` as an or-mask, which makes more sense. Change-Id: I04e5262d9ab36ae866fccd90255e4a0f85328e85 Signed-off-by:
Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51859 Reviewed-by:
Patrick Rudolph <siro@das-labor.org> Tested-by:
build bot (Jenkins) <no-reply@coreboot.org>
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Angel Pons authored
While the macro value is the same, the DMIBAR register is not HTBONUS1. Tested with BUILD_TIMELESS=1, Foxconn D41S remains identical. Change-Id: I5025f115f5a55dc782092989f3d158802d1d9353 Signed-off-by:
Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51858 Reviewed-by:
Patrick Rudolph <siro@das-labor.org> Tested-by:
build bot (Jenkins) <no-reply@coreboot.org>
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Angel Pons authored
Commit 56823f53 (nb/intel/ironlake: Rewrite early QPI init) rewrote this part, but the or-value is missing one zero. Correct this magic value to align with MRC binaries. Change-Id: Id7a6766b3f0fe415dea70cbc54afc30f808c8b16 Signed-off-by:
Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51857 Reviewed-by:
Patrick Rudolph <siro@das-labor.org> Tested-by:
build bot (Jenkins) <no-reply@coreboot.org>
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Angel Pons authored
This was copied from Sandy Bridge and does not apply to Ironlake. These offsets go past the MCHBAR window (MCHBAR size is 16 KiB on Ironlake). Some of these writes would have collided with `DEFAULT_HECIBAR` if the PCI resource had been reported as fixed. Remove the copy-pasted code. Change-Id: I7688921ad7517cbd68a0c48262b29ecf7b4c396c Signed-off-by:
Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51856 Reviewed-by:
Patrick Rudolph <siro@das-labor.org> Tested-by:
build bot (Jenkins) <no-reply@coreboot.org>
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Angel Pons authored
While 64-bit writes seem to work properly, there could be unknown side-effects in some cases, e.g. when running in long mode. Since reference code uses two 32-bit writes, follow suit. Change-Id: I48ed3d94c7865b3a3cce52108e99cf1656b57fc2 Signed-off-by:
Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51855 Reviewed-by:
Nico Huber <nico.h@gmx.de> Tested-by:
build bot (Jenkins) <no-reply@coreboot.org>
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Stanley Wu authored
Thermal sensor2 defined in baseboard do not exist in boten. With the format the DPTF policies are defined in boten, all the entries from the baseboard are included and then the overrides applied. This causes the non-existent DPTF devices to be exported in the ACPI table and in turn OS reading invalid temperatures. Fix the format for DPTF passive and critical policies. BUG=None BRANCH=dedede TEST=Build and boot to OS in boten. Ensure that the DPTF entries look correct in both static.c and SSDT tables i.e. passive and critical policies for applicable devices only are present. Change-Id: I63c781e0a439f1e7a3525fa7cf290fa9300cb066 Signed-off-by:
Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51722 Tested-by:
build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by:
Karthik Ramasubramanian <kramasub@google.com> Reviewed-by:
Ben Kao <ben.kao@intel.com> Reviewed-by:
Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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Kevin Chiu authored
Original Stamp_boost parameter will cause boost time over 2500sec(3960sec) To pass balance performance and skin temperature test, decrease stamp_boost: 2500 -> 1640 BUG=b:182753072 TEST=1. emerge-zork coreboot 2. run balance performance and skin temperature test Change-Id: I43c104ef912aafecadf9497f9ea20c8478c0e920 Signed-off-by:
Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51738 Tested-by:
build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by:
Kangheui Won <khwon@chromium.org> Reviewed-by:
Felix Held <felix-coreboot@felixheld.de>
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Sumeet R Pawnikar authored
Add processor power limits control support to configure values for alderlake soc based platforms. BRANCH=None BUG=None TEST=Build and test on alderlake rvp board Change-Id: I9dc37c7a43e6bd6f1ff5e8a97e22a0c7ac421802 Signed-off-by:
Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51397 Tested-by:
build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by:
Furquan Shaikh <furquan@google.com>
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Martin Roth authored
Updating from commit id 3a9d7cd: 2021-03-03 15:37:08 -0700 - (picasso: Update Dali SMU firmware) to commit id dded82f: 2021-03-23 15:36:36 -0600 - (picasso: Update Dali SMU firmware) This brings in 2 new commits. Signed-off-by:
Martin Roth <martin@coreboot.org> Change-Id: If71e52a2a3e50aeb8599798de7b49bc71ed26a04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51774 Tested-by:
build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by:
Marshall Dawson <marshalldawson3rd@gmail.com>
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Matt Devillier authored
On production boards, the touchpad interrupt line was moved from GPP_B20 to GPP_B3. Fix the GPIO pad config and devicetree entry, and update documentation to remove touchpad config issue. Change-Id: Iaefeba8f78c567b67e7a416c27299bff574c23ab Signed-off-by:
Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51797 Reviewed-by:
Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by:
Angel Pons <th3fanbus@gmail.com> Reviewed-by:
Furquan Shaikh <furquan@google.com> Reviewed-by:
Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by:
build bot (Jenkins) <no-reply@coreboot.org>
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Matt Devillier authored
Change-Id: Ic68a3d17534f78dae8c432253982e8d10a6427f0 Signed-off-by:
Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51550 Tested-by:
build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by:
Angel Pons <th3fanbus@gmail.com>
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Tim Wawrzynczak authored
The gpio_get_index_in_group function returns the index of the GPIO within its own group Signed-off-by:
Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I7f6b312bd1d0388ef799cd127c88b17bad6a3886 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51647 Tested-by:
build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by:
Furquan Shaikh <furquan@google.com>
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Tim Wawrzynczak authored
Signed-off-by:
Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I97203aca377d4dd77e03b2c83fdd20a2874cc1c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51755 Reviewed-by:
Furquan Shaikh <furquan@google.com> Tested-by:
build bot (Jenkins) <no-reply@coreboot.org>
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Tim Wawrzynczak authored
REG_BASE_SIZE is supposed to represent the size of the REGBAR MMIO space in KiB. It is currently sized at 4MiB, but this is incorrect, EDS Vol. 2 indicates REGBAR is 16MiB in size, therefore update the constant to reflect this. Signed-off-by:
Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I0cfbe5b8bb07faa854efd4bf70640daa117f2bb2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51754 Tested-by:
build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by:
Furquan Shaikh <furquan@google.com> Reviewed-by:
Angel Pons <th3fanbus@gmail.com>
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Tim Wawrzynczak authored
This name isn't very meaningful, rename the config option to ENABLE_TCSS_DISPLAY_DETECTION to make its meaning more obvious. Change-Id: Ib21a3b5a37d25f93bd515f8c6e5ad39c9d2ea1c4 Signed-off-by:
Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51771 Reviewed-by:
Angel Pons <th3fanbus@gmail.com> Reviewed-by:
Furquan Shaikh <furquan@google.com> Tested-by:
build bot (Jenkins) <no-reply@coreboot.org>
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Tim Wawrzynczak authored
The Type-C subsystem ("TCSS") IP block is similar between TGL and ADL. For pre-boot purposes, the limited amount of functionality required appears to be common between the two, therefore move the functionality to intel/common/block and rename from `early_tcss to `tcss` along the way. Signed-off-by:
Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I1c6bb9c7098691f0c828f9d5ab4bd522515ae966 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51753 Reviewed-by:
Furquan Shaikh <furquan@google.com> Tested-by:
build bot (Jenkins) <no-reply@coreboot.org>
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John Zhao authored
The SoC integrated address translation cache(SATC) reporting structure is added to Virtualization Technology for Directed I/O specification Rev3.2. This change adds an ACPI Name-Space Device Declaration structure SATC which has type 5 reporting structure. BUG=None TEST=Built image successfully. Signed-off-by:
John Zhao <john.zhao@intel.com> Change-Id: I91d1384083c98b75bcbdddd9cc7b7a26fab25d9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/51776 Reviewed-by: Lance Zhao Tested-by:
build bot (Jenkins) <no-reply@coreboot.org>
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lizhi7 authored
Enable gpio mode driver for ALC1015 AMP Auto Mode. BUG=b:181732574 BRANCH=dedede TEST=ALC1015Q-VB drive speaker OK Signed-off-by:
lizhi7 <lizhi7@huaqin.corp-partner.google.com> Change-Id: Idc5b190fc2c30689feaf08229b2a75c69894ac5e Reviewed-on: https://review.coreboot.org/c/coreboot/+/51763 Reviewed-by:
Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by:
Karthik Ramasubramanian <kramasub@google.com> Tested-by:
build bot (Jenkins) <no-reply@coreboot.org>
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lizhi7 authored
Enable gpio mode driver for ALC1015 AMP Auto Mode. BUG=b:177868812 BRANCH=dedede TEST=ALC1015Q-VB drive speaker OK Signed-off-by:
lizhi7 <lizhi7@huaqin.corp-partner.google.com> Change-Id: Ic7deb9be6444d85d32ff94ce8e4a140dbdea349e Reviewed-on: https://review.coreboot.org/c/coreboot/+/51732 Tested-by:
build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by:
Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by:
Karthik Ramasubramanian <kramasub@google.com>
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Tao Xia authored
Configure I2C high / low time in device tree to ensure I2C CLK runs accurately at I2C_SPEED_FAST (400 kHz). Measured I2C frequency just as below after tuning: touchpad:371.63 kHz touchpanel:368.24 kHz audio codec RT5682:369.13 kHz speaker AMP L:366.21 kHz speaker AMP R:365.8 kHz P-sensor:368.34 kHz MIPI Camera:363.35 kHz BUG=b:181589325 BRANCH=dedede TEST=Build and check after tuning I2C clock is under 400kHz Signed-off-by:
Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: I1a755a54540e106b41ac427f84989ed7e8037558 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51624 Reviewed-by:
Karthik Ramasubramanian <kramasub@google.com> Tested-by:
build bot (Jenkins) <no-reply@coreboot.org>
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Felix Held authored
This patch adds a pin configuration macro that supports both switching a pin to its native function and configuring it as a SCI source. This is a preparation to remove the GPIO2 soc_gpio_hook. Signed-off-by:
Felix Held <felix-coreboot@felixheld.de> Change-Id: If0da5c010f35fd902f6b8857368daec93c12394a Reviewed-on: https://review.coreboot.org/c/coreboot/+/50373 Reviewed-by:
Furquan Shaikh <furquan@google.com> Tested-by:
build bot (Jenkins) <no-reply@coreboot.org>
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Kevin Chiu authored
update telemetry to improve the performance. BUG=b:182753072 BRANCH=zork TEST=1. emerge-zork coreboot 2. run AMD SDLE stardust test => pass Change-Id: I6e4d0c6fcd740d82edf073fb307aa6a6b09ec78a Signed-off-by:
Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51790 Reviewed-by:
Sam McNally <sammc@google.com> Reviewed-by:
Kangheui Won <khwon@chromium.org> Tested-by:
build bot (Jenkins) <no-reply@coreboot.org>
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Matt DeVillier authored
Caroline has a Wacom W9013 digitizer on I2C2, which was incorrectly disabled in commit d957d12e [mb/google/glados: clean up variant devicetrees] as part of preparation for converting to overridetree format. Test: build/boot, verify digitizer now available under Linux Change-Id: I234bc0126b5d13c22a663d6544382890b312ce63 Signed-off-by:
Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51507 Tested-by:
build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by:
Angel Pons <th3fanbus@gmail.com>
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Maulik V Vaghela authored
List of changes: 1. Add correct board Id for ADL-M LP5 configuration 2. Add spd hex files for LP5 Micron part 3. Update memory.c file with correct Dq-dqs and byte mapping for LP5 BUG=None BRANCH=None TEST=Build is successful for ADL-M RVP Change-Id: I0bbd3f5b56bf7fbe918cc599d32a01dcae896ddd Signed-off-by:
Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50258 Tested-by:
build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by:
Angel Pons <th3fanbus@gmail.com> Reviewed-by:
Ronak Kanabar <ronak.kanabar@intel.com>
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Maulik V Vaghela authored
List of changes: 1. Add board Ids for ADL-M LP4 configuration 2. Add spd hex files for LP4 configuration 3. Update memory.c file with correct Dq-dqs and byte mapping for LP4 BUG=None BRANCH=None TEST=Build and boot is successful for ADL M LP4 RVP Change-Id: Id817faee3fff2a8a911ebda35774dfb6ddc5524b Signed-off-by:
Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50257 Reviewed-by:
Angel Pons <th3fanbus@gmail.com> Reviewed-by:
Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by:
Subrata Banik <subrata.banik@intel.com> Tested-by:
build bot (Jenkins) <no-reply@coreboot.org>
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Varshit Pandya authored
List of changes: 1. Add separate file for ADL-M GPIOs 2. Configure GPIOs as per the schematics of ADL-M RVP TEST=Able to build ADL-M Signed-off-by:
Maulik V Vaghela <maulik.v.vaghela@intel.com> Signed-off-by:
Varshit Pandya <varshit.b.pandya@intel.com> Change-Id: I03a532f69f42db723b976a0f7b0acf6f4b98e354 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49936 Tested-by:
build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by:
Angel Pons <th3fanbus@gmail.com> Reviewed-by:
Ronak Kanabar <ronak.kanabar@intel.com>
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Sridhar Siricilla authored
During the initial phases, the development and validation teams have to deal with both Consumer SKU and Lite SKU firmware. Having the support for CSE Lite enabled by default in coreboot helps in integrating both the SKUs. With this we only have to interchange the CSE region in the full BIOS image without having to worry about Kconfigs. Eases the build and integration flow. TEST=Verified build for Shadowmountain Signed-off-by:
Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I2ebf4da1b8c1df2e9c43b6e3bb688a9f8db652d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51496 Reviewed-by:
Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by:
Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by:
build bot (Jenkins) <no-reply@coreboot.org>
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Sridhar Siricilla authored
During the initial phases, the development and validation teams have to deal with both Consumer SKU and Lite SKU firmware. Having the support for CSE Lite enabled by default in coreboot helps in integrating both the SKUs. With this we only have to interchange the CSE region in the full BIOS image without having to worry about Kconfigs. Eases the build and integration flow. TEST= Built and booted on ADL-P LP4 RVP Signed-off-by:
Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: Ia92c7b71c69a23104ace9fc53fd39f01120fa751 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51567 Reviewed-by:
Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by:
Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by:
build bot (Jenkins) <no-reply@coreboot.org>
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Felix Held authored
Signed-off-by:
Felix Held <felix-coreboot@felixheld.de> Found-by: Coverity CID 1451389 Change-Id: I0af379360fc95e4c6b72d677738c6e7497ed9206 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51788 Tested-by:
build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by:
Raul Rangel <rrangel@chromium.org> Reviewed-by:
Angel Pons <th3fanbus@gmail.com>
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Jakub Czapiga authored
Some tested modules require regions to be defined but do not necessarily access them. TEST_REGION_UNALLOCATED() combined with DECLARE_REGION() are sufficient for most cases that require symbols only. Signed-off-by:
Jakub Czapiga <jacz@semihalf.com> Change-Id: I51c5f6ce56575021c6e4277a9ed17263cd2e3bb2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51769 Reviewed-by:
Julius Werner <jwerner@chromium.org> Reviewed-by:
Paul Fagerburg <pfagerburg@chromium.org> Tested-by:
build bot (Jenkins) <no-reply@coreboot.org>
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Seunghwan Kim authored
This change adds support zinitix touchpad for sasuke. BRANCH=dedede BUG=None TEST=built and checked touchpad worked on sasuke Change-Id: I85794311c49e33c4683482e125bea5ca2dbacfa8 Signed-off-by:
Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51840 Tested-by:
build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by:
Furquan Shaikh <furquan@google.com>
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Kevin Chiu authored
ALC5682 i2c address: 0x1A BUG=b:171755306 BRANCH=master TEST=emerge-grunt coreboot Change-Id: I8bc571104bebe02acf86507774580effc808beb6 Signed-off-by:
Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51708 Tested-by:
build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by:
Furquan Shaikh <furquan@google.com>
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Arthur Heymans authored
Add an option to generate the Key Manifest from Kconfig options. Change-Id: I3a448f37c81148625c7879dcb64da4d517567067 Signed-off-by:
Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50410 Reviewed-by:
Christian Walter <christian.walter@9elements.com> Tested-by:
build bot (Jenkins) <no-reply@coreboot.org>
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