purism/common/power.c: Wait 7 sec in S5 before going to DS5

Wait 7 seconds in S5 before going to DS5 state. If the SoC executes a hard reset by writing to RST_CNT (register CF9h), PCH resets by asserting SLP_S3#, SLP_S4#, and SLP_S5# for 3-5 seconds, then deasserting them.

Immediately transitioning to DS5 prevents the PCH from completing the reset, the system powers down instead. Wait 7 seconds to allow PCH to complete the reset before entering DS5. It does not appear that there is any way to specifically detect this state and wait only when a reset is intended.

Test for POWER_STATE_DS5 specifically to assert SMC_SHUTDOWN# rather than reading ALL_SYS_PWRGD_VRON. Otherwise, since ALL_SYS_PWRGD_VRON is also cleared when ALL_SYS_PWRGD is de-asserted, the system shuts off immediately.

Signed-off-by: Jonathon Hall jonathon.hall@puri.sm