This changes the clock tree from

to

 osc_25m                             10       12        0    25000000          0     0  50000
   video_pll1_ref_sel                 1        1        0    25000000          0     0  50000
       video_pll1_ref_div             1        1        0     5000000          0     0  50000
          video_pll1                  1        1        0   593999998          0     0  50000
             video_pll1_bypass        1        1        0   593999998          0     0  50000
                video_pll1_out        2        2        0   593999998          0     0  50000
                   dsi_phy_ref        1        1        0    23760000          0     0  50000

Signed-off-by: Guido Günther <agx@sigxcpu.org>