Commit 3ba333fc authored by Guido Gunther's avatar Guido Gunther
Browse files

arm64: dts: imx8mq: Add clock parent's for mixel dphy



This changes the clock tree from

to

 osc_25m                             10       12        0    25000000          0     0  50000
   video_pll1_ref_sel                 1        1        0    25000000          0     0  50000
       video_pll1_ref_div             1        1        0     5000000          0     0  50000
          video_pll1                  1        1        0   593999998          0     0  50000
             video_pll1_bypass        1        1        0   593999998          0     0  50000
                video_pll1_out        2        2        0   593999998          0     0  50000
                   dsi_phy_ref        1        1        0    23760000          0     0  50000
Signed-off-by: Guido Gunther's avatarGuido Günther <agx@sigxcpu.org>
parent 9adfa08e
...@@ -861,9 +861,14 @@ dphy: dphy@30a00300 { ...@@ -861,9 +861,14 @@ dphy: dphy@30a00300 {
reg = <0x30a00300 0x100>; reg = <0x30a00300 0x100>;
clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>; clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
clock-names = "phy_ref"; clock-names = "phy_ref";
assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>; assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>; <&clk IMX8MQ_VIDEO_PLL1_BYPASS>,
assigned-clock-rates = <24000000>; <&clk IMX8MQ_CLK_DSI_PHY_REF>,
<&clk IMX8MQ_VIDEO_PLL1>;
assigned-clock-parents = <&clk IMX8MQ_CLK_25M>,
<&clk IMX8MQ_VIDEO_PLL1>,
<&clk IMX8MQ_VIDEO_PLL1_OUT>;
assigned-clock-rates = <0>, <0>, <24000000>;
#phy-cells = <0>; #phy-cells = <0>;
power-domains = <&pgc_mipi>; power-domains = <&pgc_mipi>;
status = "disabled"; status = "disabled";
......
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