Commit d62e1f2a authored by Guido Gunther's avatar Guido Gunther
Browse files

Revert "drm/mxsfb: Update mxsfb with additional pixel formats"

This reverts commit b45ce5e0.
parent 2d54d6d2
......@@ -43,17 +43,14 @@ static u32 set_hsync_pulse_width(struct mxsfb_drm_private *mxsfb, u32 val)
}
/* Setup the MXSFB registers for decoding the pixels out of the framebuffer */
static int mxsfb_set_pixel_fmt(struct mxsfb_drm_private *mxsfb, bool update)
static int mxsfb_set_pixel_fmt(struct mxsfb_drm_private *mxsfb)
{
struct drm_crtc *crtc = &mxsfb->pipe.crtc;
struct drm_device *drm = crtc->dev;
const u32 format = crtc->primary->state->fb->format->format;
u32 ctrl = 0, ctrl1 = 0;
bool bgr_format = true;
struct drm_format_name_buf format_name_buf;
u32 ctrl, ctrl1;
if (!update)
ctrl = CTRL_BYPASS_COUNT | CTRL_MASTER;
ctrl = CTRL_BYPASS_COUNT | CTRL_MASTER;
/*
* WARNING: The bus width, CTRL_SET_BUS_WIDTH(), is configured to
......@@ -62,158 +59,64 @@ static int mxsfb_set_pixel_fmt(struct mxsfb_drm_private *mxsfb, bool update)
* to arbitrary value. This limitation should not pose an issue.
*/
if (!update) {
/* CTRL1 contains IRQ config and status bits, preserve those. */
ctrl1 = readl(mxsfb->base + LCDC_CTRL1);
ctrl1 &= CTRL1_CUR_FRAME_DONE_IRQ_EN | CTRL1_CUR_FRAME_DONE_IRQ;
}
DRM_DEV_DEBUG_DRIVER(drm->dev, "Setting up %s mode\n",
drm_get_format_name(format, &format_name_buf));
/* Do some clean-up that we might have from a previous mode */
ctrl &= ~CTRL_SHIFT_DIR(1);
ctrl &= ~CTRL_SHIFT_NUM(0x3f);
if (mxsfb->devdata->ipversion >= 4)
writel(CTRL2_ODD_LINE_PATTERN(CTRL2_LINE_PATTERN_CLR) |
CTRL2_EVEN_LINE_PATTERN(CTRL2_LINE_PATTERN_CLR),
mxsfb->base + LCDC_V4_CTRL2 + REG_CLR);
/* CTRL1 contains IRQ config and status bits, preserve those. */
ctrl1 = readl(mxsfb->base + LCDC_CTRL1);
ctrl1 &= CTRL1_CUR_FRAME_DONE_IRQ_EN | CTRL1_CUR_FRAME_DONE_IRQ;
switch (format) {
case DRM_FORMAT_BGR565: /* BG16 */
if (mxsfb->devdata->ipversion < 4)
goto err;
writel(CTRL2_ODD_LINE_PATTERN(CTRL2_LINE_PATTERN_BGR) |
CTRL2_EVEN_LINE_PATTERN(CTRL2_LINE_PATTERN_BGR),
mxsfb->base + LCDC_V4_CTRL2 + REG_SET);
/* Fall through */
case DRM_FORMAT_RGB565: /* RG16 */
case DRM_FORMAT_RGB565:
dev_dbg(drm->dev, "Setting up RGB565 mode\n");
ctrl |= CTRL_SET_WORD_LENGTH(0);
ctrl &= ~CTRL_DF16;
ctrl1 |= CTRL1_SET_BYTE_PACKAGING(0xf);
break;
case DRM_FORMAT_XBGR1555: /* XB15 */
case DRM_FORMAT_ABGR1555: /* AB15 */
if (mxsfb->devdata->ipversion < 4)
goto err;
writel(CTRL2_ODD_LINE_PATTERN(CTRL2_LINE_PATTERN_BGR) |
CTRL2_EVEN_LINE_PATTERN(CTRL2_LINE_PATTERN_BGR),
mxsfb->base + LCDC_V4_CTRL2 + REG_SET);
/* Fall through */
case DRM_FORMAT_XRGB1555: /* XR15 */
case DRM_FORMAT_ARGB1555: /* AR15 */
ctrl |= CTRL_SET_WORD_LENGTH(0);
ctrl |= CTRL_DF16;
ctrl1 |= CTRL1_SET_BYTE_PACKAGING(0xf);
break;
case DRM_FORMAT_RGBX8888: /* RX24 */
case DRM_FORMAT_RGBA8888: /* RA24 */
/* RGBX - > 0RGB */
ctrl |= CTRL_SHIFT_DIR(1);
ctrl |= CTRL_SHIFT_NUM(8);
bgr_format = false;
/* Fall through */
case DRM_FORMAT_XBGR8888: /* XB24 */
case DRM_FORMAT_ABGR8888: /* AB24 */
if (bgr_format) {
if (mxsfb->devdata->ipversion < 4)
goto err;
writel(CTRL2_ODD_LINE_PATTERN(CTRL2_LINE_PATTERN_BGR) |
CTRL2_EVEN_LINE_PATTERN(CTRL2_LINE_PATTERN_BGR),
mxsfb->base + LCDC_V4_CTRL2 + REG_SET);
}
/* Fall through */
case DRM_FORMAT_XRGB8888: /* XR24 */
case DRM_FORMAT_ARGB8888: /* AR24 */
case DRM_FORMAT_XRGB8888:
dev_dbg(drm->dev, "Setting up XRGB8888 mode\n");
ctrl |= CTRL_SET_WORD_LENGTH(3);
/* Do not use packed pixels = one pixel per word instead. */
ctrl1 |= CTRL1_SET_BYTE_PACKAGING(0x7);
break;
default:
goto err;
dev_err(drm->dev, "Unhandled pixel format %08x\n", format);
return -EINVAL;
}
if (update) {
writel(ctrl, mxsfb->base + LCDC_CTRL + REG_SET);
writel(ctrl1, mxsfb->base + LCDC_CTRL1 + REG_SET);
} else {
writel(ctrl, mxsfb->base + LCDC_CTRL);
writel(ctrl1, mxsfb->base + LCDC_CTRL1);
}
writel(ctrl1, mxsfb->base + LCDC_CTRL1);
writel(ctrl, mxsfb->base + LCDC_CTRL);
return 0;
err:
DRM_DEV_ERROR(drm->dev, "Unhandled pixel format: %s\n",
drm_get_format_name(format, &format_name_buf));
return -EINVAL;
}
static u32 get_bus_format_from_bpp(u32 bpp)
{
switch (bpp) {
case 16:
return MEDIA_BUS_FMT_RGB565_1X16;
case 18:
return MEDIA_BUS_FMT_RGB666_1X18;
case 24:
return MEDIA_BUS_FMT_RGB888_1X24;
default:
return MEDIA_BUS_FMT_RGB888_1X24;
}
}
static void mxsfb_set_bus_fmt(struct mxsfb_drm_private *mxsfb)
{
struct drm_crtc *crtc = &mxsfb->pipe.crtc;
unsigned int bits_per_pixel = crtc->primary->state->fb->format->depth;
struct drm_device *drm = crtc->dev;
u32 bus_format = MEDIA_BUS_FMT_RGB888_1X24;
int num_bus_formats = mxsfb->connector->display_info.num_bus_formats;
const u32 *bus_formats = mxsfb->connector->display_info.bus_formats;
u32 reg = 0;
int i = 0;
/* match the user requested bus_format to one supported by the panel */
if (num_bus_formats) {
u32 user_bus_format = get_bus_format_from_bpp(bits_per_pixel);
bus_format = bus_formats[0];
for (i = 0; i < num_bus_formats; i++) {
if (user_bus_format == bus_formats[i]) {
bus_format = user_bus_format;
break;
}
}
}
u32 reg;
/*
* CRTC will dictate the bus format via private_flags[16:1]
* and private_flags[0] will signal a bus format change
*/
crtc->mode.private_flags &= ~0x1FFFF; /* clear bus format */
crtc->mode.private_flags |= (bus_format << 1); /* set bus format */
crtc->mode.private_flags |= 0x1; /* bus format change indication*/
reg = readl(mxsfb->base + LCDC_CTRL);
if (mxsfb->connector->display_info.num_bus_formats)
bus_format = mxsfb->connector->display_info.bus_formats[0];
DRM_DEV_DEBUG_DRIVER(drm->dev, "Using bus_format: 0x%08X\n",
bus_format);
reg &= ~CTRL_BUS_WIDTH_MASK;
switch (bus_format) {
case MEDIA_BUS_FMT_RGB565_1X16:
reg = CTRL_SET_BUS_WIDTH(STMLCDIF_16BIT);
reg |= CTRL_SET_BUS_WIDTH(STMLCDIF_16BIT);
break;
case MEDIA_BUS_FMT_RGB666_1X18:
reg = CTRL_SET_BUS_WIDTH(STMLCDIF_18BIT);
reg |= CTRL_SET_BUS_WIDTH(STMLCDIF_18BIT);
break;
case MEDIA_BUS_FMT_RGB888_1X24:
reg = CTRL_SET_BUS_WIDTH(STMLCDIF_24BIT);
reg |= CTRL_SET_BUS_WIDTH(STMLCDIF_24BIT);
break;
default:
dev_err(drm->dev, "Unknown media bus format %d\n", bus_format);
break;
}
writel(reg, mxsfb->base + LCDC_CTRL + REG_SET);
writel(reg, mxsfb->base + LCDC_CTRL);
}
static void mxsfb_enable_controller(struct mxsfb_drm_private *mxsfb)
......@@ -348,7 +251,7 @@ static void mxsfb_crtc_mode_set_nofb(struct mxsfb_drm_private *mxsfb)
/* Clear the FIFOs */
writel(CTRL1_FIFO_CLEAR, mxsfb->base + LCDC_CTRL1 + REG_SET);
err = mxsfb_set_pixel_fmt(mxsfb, false);
err = mxsfb_set_pixel_fmt(mxsfb);
if (err)
return;
......
......@@ -47,27 +47,6 @@ enum mxsfb_devtype {
MXSFB_V4,
};
/*
* When adding new formats, make sure to update the num_formats from
* mxsfb_devdata below.
*/
static const u32 mxsfb_formats[] = {
/* MXSFB_V3 */
DRM_FORMAT_XRGB8888,
DRM_FORMAT_ARGB8888,
DRM_FORMAT_RGB565,
/* MXSFB_V4 */
DRM_FORMAT_XBGR8888,
DRM_FORMAT_ABGR8888,
DRM_FORMAT_RGBX8888,
DRM_FORMAT_RGBA8888,
DRM_FORMAT_ARGB1555,
DRM_FORMAT_XRGB1555,
DRM_FORMAT_ABGR1555,
DRM_FORMAT_XBGR1555,
DRM_FORMAT_BGR565
};
static const struct mxsfb_devdata mxsfb_devdata[] = {
[MXSFB_V3] = {
.transfer_count = LCDC_V3_TRANSFER_COUNT,
......@@ -77,7 +56,6 @@ static const struct mxsfb_devdata mxsfb_devdata[] = {
.hs_wdth_mask = 0xff,
.hs_wdth_shift = 24,
.ipversion = 3,
.num_formats = 3,
},
[MXSFB_V4] = {
.transfer_count = LCDC_V4_TRANSFER_COUNT,
......@@ -87,10 +65,14 @@ static const struct mxsfb_devdata mxsfb_devdata[] = {
.hs_wdth_mask = 0x3fff,
.hs_wdth_shift = 18,
.ipversion = 4,
.num_formats = ARRAY_SIZE(mxsfb_formats),
},
};
static const uint32_t mxsfb_formats[] = {
DRM_FORMAT_XRGB8888,
DRM_FORMAT_RGB565
};
static struct mxsfb_drm_private *
drm_pipe_to_mxsfb_drm_private(struct drm_simple_display_pipe *pipe)
{
......@@ -354,7 +336,7 @@ static int mxsfb_load(struct drm_device *drm, unsigned long flags)
}
ret = drm_simple_display_pipe_init(drm, &mxsfb->pipe, &mxsfb_funcs,
mxsfb_formats, mxsfb->devdata->num_formats, NULL,
mxsfb_formats, ARRAY_SIZE(mxsfb_formats), NULL,
mxsfb->connector);
if (ret < 0) {
dev_err(drm->dev, "Cannot setup simple display pipe\n");
......
......@@ -16,7 +16,6 @@ struct mxsfb_devdata {
unsigned int hs_wdth_mask;
unsigned int hs_wdth_shift;
unsigned int ipversion;
unsigned int num_formats;
};
struct mxsfb_drm_private {
......@@ -42,6 +41,6 @@ int mxsfb_create_output(struct drm_device *dev);
void mxsfb_crtc_enable(struct mxsfb_drm_private *mxsfb);
void mxsfb_crtc_disable(struct mxsfb_drm_private *mxsfb);
void mxsfb_plane_atomic_update(struct mxsfb_drm_private *mxsfb,
struct drm_plane_state *old_state);
struct drm_plane_state *state);
#endif /* __MXSFB_DRV_H__ */
......@@ -44,11 +44,6 @@
#define REG_PUT(x, h, l) (((x) << (l)) & GENMASK(h, l))
#define REG_GET(x, h, l) (((x) & GENMASK(h, l)) >> (l))
#define SWIZZLE_LE 0 /* Little-Endian or No swap */
#define SWIZZLE_BE 1 /* Big-Endian or swap all */
#define SWIZZLE_HWD 2 /* Swap half-words */
#define SWIZZLE_HWD_BYTE 3 /* Swap bytes within each half-word */
#define CTRL_SFTRST BIT(31)
#define CTRL_CLKGATE BIT(30)
#define CTRL_SHIFT_DIR(x) REG_PUT((x), 26, 26)
......
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