Commit e3722284 authored by Guido Gunther's avatar Guido Gunther

Merge branch 'refs/heads/forward-upstream/next-20191018/mxsfb+nwl/v7' into...

Merge branch 'refs/heads/forward-upstream/next-20191018/mxsfb+nwl/v7' into f/next-20191018/devkit-drm-integration/v1-wip-Aev0fe7AhD2j

* refs/heads/forward-upstream/next-20191018/mxsfb+nwl/v7: (33 commits)
  nwl: Disable reset quirk
  Revert "drm/mxsfb: Add support for horizontal stride"
  Revert "drm/mxsfb: Add support for live pixel format change"
  Revert "drm/mxsfb: Update mxsfb with additional pixel formats"
  drm/bridge: Add NWL MIPI DSI host controller support
  dt-bindings: display/bridge: Add binding for NWL mipi dsi host controller
  dts: arm64: devkit: adjust device tree
  arm64: dts: imx8mq: Init rates and parents configs for clocks
  librem5-devkit: Enable multiplexer in defconfig
  drm/mxsfb: Add support for live pixel format change
  drm/mxsfb: Add support for horizontal stride
  drm/mxsfb: Clear OUTSTANDING_REQS bits
  drm/mxsfb: Improve the axi clock usage
  drm/mxsfb: Update mxsfb to support LCD reset
  dt-bindings: display: Add max-memory-bandwidth property for mxsfb
  drm/mxsfb: Add max-memory-bandwidth property for MXSFB
  drm/mxsfb: Signal mode changed when bpp changed
  drm/mxsfb: Fix the vblank events
  drm/mxsfb: Update mxsfb with additional pixel formats
  drm/mxsfb: Update register definitions using bit manipulation defines
  ...
parents 8d1a1e4c 107b8fd4
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/nwl-dsi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Northwest Logic MIPI-DSI controller on i.MX SoCs
maintainers:
- Guido Gúnther <agx@sigxcpu.org>
- Robert Chiras <robert.chiras@nxp.com>
description: |
NWL MIPI-DSI host controller found on i.MX8 platforms. This is a dsi bridge for
the SOCs NWL MIPI-DSI host controller.
properties:
compatible:
const: fsl,imx8mq-nwl-dsi
reg:
maxItems: 1
interrupts:
maxItems: 1
'#address-cells':
const: 1
'#size-cells':
const: 0
clocks:
items:
- description: DSI core clock
- description: RX_ESC clock (used in escape mode)
- description: TX_ESC clock (used in escape mode)
- description: PHY_REF clock
clock-names:
items:
- const: core
- const: rx_esc
- const: tx_esc
- const: phy_ref
mux-controls:
description:
mux controller node to use for operating the input mux
phys:
maxItems: 1
description:
A phandle to the phy module representing the DPHY
phy-names:
items:
- const: dphy
power-domains:
maxItems: 1
resets:
items:
- description: dsi byte reset line
- description: dsi dpi reset line
- description: dsi esc reset line
- description: dsi pclk reset line
reset-names:
items:
- const: byte
- const: dpi
- const: esc
- const: pclk
ports:
type: object
description:
A node containing DSI input & output port nodes with endpoint
definitions as documented in
Documentation/devicetree/bindings/graph.txt.
properties:
port@0:
type: object
description:
Input port node to receive pixel data from the
display controller. Exactly one endpoint must be
specified.
properties:
'#address-cells':
const: 1
'#size-cells':
const: 0
endpoint@0:
description: sub-node describing the input from LCDIF
type: object
endpoint@1:
description: sub-node describing the input from DCSS
type: object
reg:
const: 0
required:
- '#address-cells'
- '#size-cells'
- reg
additionalProperties: false
port@1:
type: object
description:
DSI output port node to the panel or the next bridge
in the chain
'#address-cells':
const: 1
'#size-cells':
const: 0
required:
- '#address-cells'
- '#size-cells'
- port@0
- port@1
additionalProperties: false
patternProperties:
"^panel@[0-9]+$":
type: object
required:
- '#address-cells'
- '#size-cells'
- clock-names
- clocks
- compatible
- interrupts
- mux-controls
- phy-names
- phys
- ports
- reg
- reset-names
- resets
additionalProperties: false
examples:
- |
mipi_dsi: mipi_dsi@30a00000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx8mq-nwl-dsi";
reg = <0x30A00000 0x300>;
clocks = <&clk 163>, <&clk 244>, <&clk 245>, <&clk 164>;
clock-names = "core", "rx_esc", "tx_esc", "phy_ref";
interrupts = <0 34 4>;
mux-controls = <&mux 0>;
power-domains = <&pgc_mipi>;
resets = <&src 0>, <&src 1>, <&src 2>, <&src 3>;
reset-names = "byte", "dpi", "esc", "pclk";
phys = <&dphy>;
phy-names = "dphy";
panel@0 {
compatible = "rocktech,jh057n00900";
reg = <0>;
port@0 {
panel_in: endpoint {
remote-endpoint = <&mipi_dsi_out>;
};
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
#size-cells = <0>;
#address-cells = <1>;
reg = <0>;
mipi_dsi_in: endpoint@0 {
reg = <0>;
remote-endpoint = <&lcdif_mipi_dsi>;
};
};
port@1 {
reg = <1>;
mipi_dsi_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
};
......@@ -14,6 +14,11 @@ Required properties:
- "pix" for the LCDIF block clock
- (MX6SX-only) "axi", "disp_axi" for the bus interface clock
Optional properties:
- max-memory-bandwidth: maximum bandwidth in bytes per second that the
controller can handle; if not present, the memory
interface is fast enough to handle all possible video modes
Required sub-nodes:
- port: The connection to an encoder chip.
......
......@@ -23,7 +23,6 @@ backlight_dsi: backlight-dsi {
/* Default brightness level (index into the array defined by */
/* the "brightness-levels" property) */
default-brightness-level = <0>;
power-supply = <&reg_22v4_p>;
};
chosen {
......@@ -169,11 +168,6 @@ wifi_pwr_en: regulator-wifi-en {
};
};
&clk {
assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL2>;
assigned-clock-rates = <786432000>, <722534400>;
};
&dphy {
status = "okay";
};
......@@ -407,6 +401,15 @@ charger@6b { /* bq25896 */
ti,boost-voltage = <5000000>; /* 5V */
ti,boost-max-current = <50000>; /* 50mA */
};
prox@60 {
compatible = "vishay,vcnl4040", "vishay,vcnl4200";
reg = <0x60>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_prox>;
interrupt-parent = <&gpio1>;
interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
};
};
&i2c3 {
......@@ -536,6 +539,12 @@ MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x80 /* PMIC intr */
>;
};
pinctrl_prox: proxgrp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x80 /* PROX_INT */
>;
};
pinctrl_pwr_en: pwrengrp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x06
......@@ -705,12 +714,67 @@ MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19 /* WWAN_RESET */
};
};
&lcdif {
status = "okay";
max-res = <720>, <1440>;
port@0 {
lcdif_mipi_dsi: endpoint {
remote-endpoint = <&mipi_dsi_lcdif_in>;
};
};
};
&mipi_dsi {
status = "okay";
panel@0 {
compatible = "rocktech,jh057n00900";
reg = <0>;
backlight = <&backlight_dsi>;
reset-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>;
vcc-supply = <&reg_2v8_p>;
iovcc-supply = <&reg_1v8_p>;
port@0 {
panel_in: endpoint {
remote-endpoint = <&mipi_dsi_out>;
};
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
#size-cells = <0>;
#address-cells = <1>;
reg = <0>;
mipi_dsi_lcdif_in: endpoint@0 {
reg = <0>;
remote-endpoint = <&lcdif_mipi_dsi>;
};
/*
mipi_dsi_dcss_in: endpoint@1 {
reg = <1>;
remote-endpoint = <&dcss_mipi_dsi>;
};
*/
};
port@1 {
reg = <1>;
mipi_dsi_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
};
&pgc_gpu {
power-supply = <&buck3_reg>;
//power-supply = <&buck3_reg>;
};
&pgc_vpu {
power-supply = <&buck4_reg>;
//power-supply = <&buck4_reg>;
};
&pwm1 {
......
......@@ -460,6 +460,24 @@ sdma2: sdma@302c0000 {
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
};
lcdif: lcdif@30320000 {
compatible = "fsl,imx8mq-lcdif", "fsl,imx28-lcdif";
reg = <0x30320000 0x10000>;
clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>;
clock-names = "pix";
assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
<&clk IMX8MQ_VIDEO_PLL1_BYPASS>,
<&clk IMX8MQ_CLK_LCDIF_PIXEL>,
<&clk IMX8MQ_VIDEO_PLL1>;
assigned-clock-parents = <&clk IMX8MQ_CLK_25M>,
<&clk IMX8MQ_VIDEO_PLL1>,
<&clk IMX8MQ_VIDEO_PLL1_OUT>;
assigned-clock-rates = <0>, <0>, <0>, <594000000>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
max-res = <1280>, <720>;
status = "disabled";
};
iomuxc: iomuxc@30330000 {
compatible = "fsl,imx8mq-iomuxc";
reg = <0x30330000 0x10000>;
......@@ -531,6 +549,27 @@ clk: clock-controller@30380000 {
clock-names = "ckil", "osc_25m", "osc_27m",
"clk_ext1", "clk_ext2",
"clk_ext3", "clk_ext4";
assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1>,
<&clk IMX8MQ_AUDIO_PLL1>,
<&clk IMX8MQ_AUDIO_PLL2>,
<&clk IMX8MQ_CLK_AHB>,
<&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
<&clk IMX8MQ_CLK_AUDIO_AHB>,
<&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
<&clk IMX8MQ_CLK_NOC>;
assigned-clock-parents = <0>,
<0>,
<0>,
<&clk IMX8MQ_SYS1_PLL_133M>,
<&clk IMX8MQ_SYS1_PLL_266M>,
<&clk IMX8MQ_SYS2_PLL_500M>,
<&clk IMX8MQ_CLK_27M>,
<&clk IMX8MQ_SYS1_PLL_800M>;
assigned-clock-rates = <593999999>,
<786432000>,
<722534400>;
};
src: reset-controller@30390000 {
......@@ -807,14 +846,50 @@ sec_jr2: jr@3000 {
};
};
mipi_dsi: mipi_dsi@30a00000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx8mq-nwl-dsi";
reg = <0x30a00000 0x300>;
clocks = <&clk IMX8MQ_CLK_DSI_CORE>,
<&clk IMX8MQ_CLK_DSI_AHB>,
<&clk IMX8MQ_CLK_DSI_IPG_DIV>,
<&clk IMX8MQ_CLK_DSI_PHY_REF>;
clock-names = "core", "rx_esc", "tx_esc", "phy_ref";
assigned-clocks = <&clk IMX8MQ_CLK_DSI_AHB>,
<&clk IMX8MQ_CLK_DSI_CORE>,
<&clk IMX8MQ_CLK_DSI_IPG_DIV>;
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>,
<&clk IMX8MQ_SYS1_PLL_266M>;
assigned-clock-rates = <80000000>,
<266000000>,
<20000000>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pgc_mipi>;
resets = <&src IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N>,
<&src IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N>,
<&src IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N>,
<&src IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N>;
reset-names = "byte", "dpi", "esc", "pclk";
mux-controls = <&mux 0>;
phys = <&dphy>;
phy-names = "dphy";
status = "disabled";
};
dphy: dphy@30a00300 {
compatible = "fsl,imx8mq-mipi-dphy";
reg = <0x30a00300 0x100>;
clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
clock-names = "phy_ref";
assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>;
assigned-clock-rates = <24000000>;
assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
<&clk IMX8MQ_VIDEO_PLL1_BYPASS>,
<&clk IMX8MQ_CLK_DSI_PHY_REF>,
<&clk IMX8MQ_VIDEO_PLL1>;
assigned-clock-parents = <&clk IMX8MQ_CLK_25M>,
<&clk IMX8MQ_VIDEO_PLL1>,
<&clk IMX8MQ_VIDEO_PLL1_OUT>;
assigned-clock-rates = <0>, <0>, <24000000>;
#phy-cells = <0>;
power-domains = <&pgc_mipi>;
status = "disabled";
......
......@@ -394,6 +394,8 @@ CONFIG_DRM_I2C_CH7006=m
CONFIG_DRM_I2C_SIL164=m
CONFIG_DRM_I2C_NXP_TDA9950=m
CONFIG_DRM_PANEL_SIMPLE=m
CONFIG_DRM_PANEL_ROCKTECH_JH057N00900=y
CONFIG_DRM_NWL_MIPI_DSI=y
CONFIG_DRM_ETNAVIV=y
CONFIG_DRM_MXSFB=y
CONFIG_FB_ARMCLCD=y
......@@ -524,7 +526,7 @@ CONFIG_PHY_FSL_IMX8MQ_USB=m
CONFIG_PHY_MIXEL_MIPI_DPHY=y
CONFIG_POWERCAP=y
CONFIG_NVMEM_IMX_OCOTP=y
CONFIG_PHY_MIXEL_MIPI_DPHY=y
CONFIG_MUX_MMIO=y
CONFIG_EXT2_FS=y
CONFIG_EXT3_FS=y
CONFIG_EXT4_FS_POSIX_ACL=y
......
......@@ -65,6 +65,22 @@ config DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW
to DP++. This is used with the i.MX6 imx-ldb
driver. You are likely to say N here.
config DRM_NWL_MIPI_DSI
tristate "Northwest Logic MIPI DSI Host controller"
depends on DRM
depends on COMMON_CLK
depends on OF && HAS_IOMEM
select DRM_KMS_HELPER
select DRM_MIPI_DSI
select DRM_PANEL_BRIDGE
select GENERIC_PHY_MIPI_DPHY
select MFD_SYSCON
select MULTIPLEXER
select REGMAP_MMIO
help
This enables the Northwest Logic MIPI DSI Host controller as
for example found on NXP's i.MX8 Processors.
config DRM_NXP_PTN3460
tristate "NXP PTN3460 DP/LVDS bridge"
depends on OF
......
......@@ -16,4 +16,7 @@ obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix/
obj-$(CONFIG_DRM_I2C_ADV7511) += adv7511/
obj-$(CONFIG_DRM_TI_SN65DSI86) += ti-sn65dsi86.o
obj-$(CONFIG_DRM_TI_TFP410) += ti-tfp410.o
obj-$(CONFIG_DRM_NWL_MIPI_DSI) += nwl-dsi.o
obj-y += synopsys/
header-test-y += nwl-dsi.h
This diff is collapsed.
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* NWL MIPI DSI host driver
*
* Copyright (C) 2017 NXP
* Copyright (C) 2019 Purism SPC
*/
#ifndef __NWL_DSI_H__
#define __NWL_DSI_H__
/* DSI HOST registers */
#define NWL_DSI_CFG_NUM_LANES 0x0
#define NWL_DSI_CFG_NONCONTINUOUS_CLK 0x4
#define NWL_DSI_CFG_T_PRE 0x8
#define NWL_DSI_CFG_T_POST 0xc
#define NWL_DSI_CFG_TX_GAP 0x10
#define NWL_DSI_CFG_AUTOINSERT_EOTP 0x14
#define NWL_DSI_CFG_EXTRA_CMDS_AFTER_EOTP 0x18
#define NWL_DSI_CFG_HTX_TO_COUNT 0x1c
#define NWL_DSI_CFG_LRX_H_TO_COUNT 0x20
#define NWL_DSI_CFG_BTA_H_TO_COUNT 0x24
#define NWL_DSI_CFG_TWAKEUP 0x28
#define NWL_DSI_CFG_STATUS_OUT 0x2c
#define NWL_DSI_RX_ERROR_STATUS 0x30
/* DSI DPI registers */
#define NWL_DSI_PIXEL_PAYLOAD_SIZE 0x200
#define NWL_DSI_PIXEL_FIFO_SEND_LEVEL 0x204
#define NWL_DSI_INTERFACE_COLOR_CODING 0x208
#define NWL_DSI_PIXEL_FORMAT 0x20c
#define NWL_DSI_VSYNC_POLARITY 0x210
#define NWL_DSI_VSYNC_POLARITY_ACTIVE_LOW 0
#define NWL_DSI_VSYNC_POLARITY_ACTIVE_HIGH BIT(1)
#define NWL_DSI_HSYNC_POLARITY 0x214
#define NWL_DSI_HSYNC_POLARITY_ACTIVE_LOW 0
#define NWL_DSI_HSYNC_POLARITY_ACTIVE_HIGH BIT(1)
#define NWL_DSI_VIDEO_MODE 0x218
#define NWL_DSI_HFP 0x21c
#define NWL_DSI_HBP 0x220
#define NWL_DSI_HSA 0x224
#define NWL_DSI_ENABLE_MULT_PKTS 0x228
#define NWL_DSI_VBP 0x22c
#define NWL_DSI_VFP 0x230
#define NWL_DSI_BLLP_MODE 0x234
#define NWL_DSI_USE_NULL_PKT_BLLP 0x238
#define NWL_DSI_VACTIVE 0x23c
#define NWL_DSI_VC 0x240
/* DSI APB PKT control */
#define NWL_DSI_TX_PAYLOAD 0x280
#define NWL_DSI_PKT_CONTROL 0x284
#define NWL_DSI_SEND_PACKET 0x288
#define NWL_DSI_PKT_STATUS 0x28c
#define NWL_DSI_PKT_FIFO_WR_LEVEL 0x290
#define NWL_DSI_PKT_FIFO_RD_LEVEL 0x294
#define NWL_DSI_RX_PAYLOAD 0x298
#define NWL_DSI_RX_PKT_HEADER 0x29c
/* DSI IRQ handling */
#define NWL_DSI_IRQ_STATUS 0x2a0
#define NWL_DSI_SM_NOT_IDLE BIT(0)
#define NWL_DSI_TX_PKT_DONE BIT(1)
#define NWL_DSI_DPHY_DIRECTION BIT(2)
#define NWL_DSI_TX_FIFO_OVFLW BIT(3)
#define NWL_DSI_TX_FIFO_UDFLW BIT(4)
#define NWL_DSI_RX_FIFO_OVFLW BIT(5)
#define NWL_DSI_RX_FIFO_UDFLW BIT(6)
#define NWL_DSI_RX_PKT_HDR_RCVD BIT(7)
#define NWL_DSI_RX_PKT_PAYLOAD_DATA_RCVD BIT(8)
#define NWL_DSI_BTA_TIMEOUT BIT(29)
#define NWL_DSI_LP_RX_TIMEOUT BIT(30)
#define NWL_DSI_HS_TX_TIMEOUT BIT(31)
#define NWL_DSI_IRQ_STATUS2 0x2a4
#define NWL_DSI_SINGLE_BIT_ECC_ERR BIT(0)
#define NWL_DSI_MULTI_BIT_ECC_ERR BIT(1)
#define NWL_DSI_CRC_ERR BIT(2)
#define NWL_DSI_IRQ_MASK 0x2a8
#define NWL_DSI_SM_NOT_IDLE_MASK BIT(0)
#define NWL_DSI_TX_PKT_DONE_MASK BIT(1)
#define NWL_DSI_DPHY_DIRECTION_MASK BIT(2)
#define NWL_DSI_TX_FIFO_OVFLW_MASK BIT(3)
#define NWL_DSI_TX_FIFO_UDFLW_MASK BIT(4)
#define NWL_DSI_RX_FIFO_OVFLW_MASK BIT(5)
#define NWL_DSI_RX_FIFO_UDFLW_MASK BIT(6)
#define NWL_DSI_RX_PKT_HDR_RCVD_MASK BIT(7)
#define NWL_DSI_RX_PKT_PAYLOAD_DATA_RCVD_MASK BIT(8)
#define NWL_DSI_BTA_TIMEOUT_MASK BIT(29)
#define NWL_DSI_LP_RX_TIMEOUT_MASK BIT(30)
#define NWL_DSI_HS_TX_TIMEOUT_MASK BIT(31)
#define NWL_DSI_IRQ_MASK2 0x2ac
#define NWL_DSI_SINGLE_BIT_ECC_ERR_MASK BIT(0)
#define NWL_DSI_MULTI_BIT_ECC_ERR_MASK BIT(1)
#define NWL_DSI_CRC_ERR_MASK BIT(2)
/*
* PKT_CONTROL format:
* [15: 0] - word count
* [17:16] - virtual channel
* [23:18] - data type
* [24] - LP or HS select (0 - LP, 1 - HS)
* [25] - perform BTA after packet is sent
* [26] - perform BTA only, no packet tx
*/
#define NWL_DSI_WC(x) FIELD_PREP(GENMASK(15, 0), (x))
#define NWL_DSI_TX_VC(x) FIELD_PREP(GENMASK(17, 16), (x))
#define NWL_DSI_TX_DT(x) FIELD_PREP(GENMASK(23, 18), (x))
#define NWL_DSI_HS_SEL(x) FIELD_PREP(GENMASK(24, 24), (x))
#define NWL_DSI_BTA_TX(x) FIELD_PREP(GENMASK(25, 25), (x))
#define NWL_DSI_BTA_NO_TX(x) FIELD_PREP(GENMASK(26, 26), (x))
/*
* RX_PKT_HEADER format:
* [15: 0] - word count
* [21:16] - data type
* [23:22] - virtual channel
*/
#define NWL_DSI_RX_DT(x) FIELD_GET(GENMASK(21, 16), (x))
#define NWL_DSI_RX_VC(x) FIELD_GET(GENMASK(23, 22), (x))
/* DSI Video mode */
#define NWL_DSI_VM_BURST_MODE_WITH_SYNC_PULSES 0