- 22 Oct, 2019 14 commits
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Guido Gunther authored
Signed-off-by:
Guido Günther <guido.gunther@puri.sm>
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Guido Gunther authored
This reverts commit f4a30d83.
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Guido Gunther authored
Otherwise it breaks mipi Signed-off-by:
Guido Günther <guido.gunther@puri.sm>
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Guido Gunther authored
This reverts commit 87059726.
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Guido Gunther authored
Signed-off-by:
Guido Günther <guido.gunther@puri.sm>
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Guido Gunther authored
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Guido Gunther authored
Merge branch 'refs/heads/forward-upstream/next-20191018/touch-config/v0-wip' into f/next-20191018/devkit-drm-integration/v1-wip-Aev0fe7AhD2j * refs/heads/forward-upstream/next-20191018/touch-config/v0-wip: librem5-devkit: Enable touchscreen input: touchscreen: Selelct TOUCHSCREEN_PROPERTIES for drivers using it librem5-devkit_defconfig: Enable imx8 mixel dphy
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Guido Gunther authored
Merge branch 'refs/heads/forward-upstream/next-20191018/mxsfb+nwl/v7' into f/next-20191018/devkit-drm-integration/v1-wip-Aev0fe7AhD2j * refs/heads/forward-upstream/next-20191018/mxsfb+nwl/v7: (33 commits) nwl: Disable reset quirk Revert "drm/mxsfb: Add support for horizontal stride" Revert "drm/mxsfb: Add support for live pixel format change" Revert "drm/mxsfb: Update mxsfb with additional pixel formats" drm/bridge: Add NWL MIPI DSI host controller support dt-bindings: display/bridge: Add binding for NWL mipi dsi host controller dts: arm64: devkit: adjust device tree arm64: dts: imx8mq: Init rates and parents configs for clocks librem5-devkit: Enable multiplexer in defconfig drm/mxsfb: Add support for live pixel format change drm/mxsfb: Add support for horizontal stride drm/mxsfb: Clear OUTSTANDING_REQS bits drm/mxsfb: Improve the axi clock usage drm/mxsfb: Update mxsfb to support LCD reset dt-bindings: display: Add max-memory-bandwidth property for mxsfb drm/mxsfb: Add max-memory-bandwidth property for MXSFB drm/mxsfb: Signal mode changed when bpp changed drm/mxsfb: Fix the vblank events drm/mxsfb: Update mxsfb with additional pixel formats drm/mxsfb: Update register definitions using bit manipulation defines ...
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Guido Gunther authored
Merge branch 'refs/heads/forward-upstream/next-20191018/imx8-soc-info/v2-wip' into f/next-20191018/devkit-drm-integration/v1-wip-Aev0fe7AhD2j * refs/heads/forward-upstream/next-20191018/imx8-soc-info/v2-wip: soc: imx: Try harder to get imx8mq SoC revisions librem5-devkit_defconfig: Enable imx8 mixel dphy
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Guido Gunther authored
Merge branch 'refs/heads/forward-upstream/next-20191018/gpu-thermal/v2' into f/next-20191018/devkit-drm-integration/v1-wip-Aev0fe7AhD2j * refs/heads/forward-upstream/next-20191018/gpu-thermal/v2: dt-bindings: etnaviv: Add #cooling-cells librem5-devkit_defconfig: Enable imx8 mixel dphy
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Guido Gunther authored
Signed-off-by:
Guido Günther <guido.gunther@puri.sm>
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Guido Gunther authored
This reverts commit 4cbaf59b.
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Guido Gunther authored
This reverts commit 81588e44.
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Guido Gunther authored
This reverts commit b45ce5e0.
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- 19 Oct, 2019 3 commits
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Guido Gunther authored
This adds initial support for the NWL MIPI DSI Host controller found on i.MX8 SoCs. It adds support for the i.MX8MQ but the same IP can be found on e.g. the i.MX8QXP. It has been tested on the Librem 5 devkit using mxsfb. Signed-off-by:
Guido Günther <agx@sigxcpu.org> Co-developed-by:
Robert Chiras <robert.chiras@nxp.com> Signed-off-by:
Robert Chiras <robert.chiras@nxp.com> Tested-by:
Robert Chiras <robert.chiras@nxp.com>
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Guido Gunther authored
The Northwest Logic MIPI DSI IP core can be found in NXPs i.MX8 SoCs. Signed-off-by:
Guido Günther <agx@sigxcpu.org> Tested-by:
Robert Chiras <robert.chiras@nxp.com> Reviewed-by:
Rob Herring <robh@kernel.org>
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Guido Gunther authored
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- 18 Oct, 2019 23 commits
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Guido Gunther authored
Signed-off-by:
Guido Günther <guido.gunther@puri.sm>
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Guido Gunther authored
Otherwise we might end up with modules that can't be loaded: modprobe: ERROR: could not insert 'goodix': Unknown symbol in module, or unknown parameter (see dmesg) [ 15.190397] goodix: Unknown symbol touchscreen_report_pos (err -2) [ 15.221560] goodix: Unknown symbol touchscreen_parse_properties (err -2) [ 64.677545] goodix: Unknown symbol touchscreen_report_pos (err -2) [ 64.683767] goodix: Unknown symbol touchscreen_parse_properties (err -2) Signed-off-by:
Guido Günther <agx@sigxcpu.org>
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Guido Gunther authored
Signed-off-by:
Guido Günther <guido.gunther@puri.sm>
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Abel Vesa authored
Add the initial configuration for clocks that need default parent and rate setting. This is based on the vendor tree clock provider parents and rates configuration except this is doing the setup in dts rather then using clock consumer API in a clock provider driver. Note that by adding the initial rate setting for audio_pll1/audio_pll setting we need to remove it from imx8mq-librem5-devkit.dts imx8mq-librem5-devkit.dts Signed-off-by:
Abel Vesa <abel.vesa@nxp.com> Signed-off-by:
Daniel Baluta <daniel.baluta@nxp.com>
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Guido Gunther authored
(todo: check if generic arm64 config has it) Signed-off-by:
Guido Günther <guido.gunther@puri.sm>
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Robert Chiras authored
This IP requires full stop and re-start when changing display timings, but we can change the pixel format while running. Signed-off-by:
Robert Chiras <robert.chiras@nxp.com>
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Robert Chiras authored
Besides the eLCDIF block, there is another IP block, used in the past for EPDC panels. Since the iMX.8mq doesn't have an EPDC connector, this block is not documented, but we can use it to do additional operations on the frame buffer. In this case, we can use the pigeon registers from this IP block in order to do horizontal crop on the frame buffer processed by the eLCDIF block. Signed-off-by:
Robert Chiras <robert.chiras@nxp.com>
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Robert Chiras authored
Bit 21 can alter the CTRL2_OUTSTANDING_REQS value right after the eLCDIF is enabled, since it comes up with default value of 1 (this behaviour has been seen on some imx8 platforms). In order to fix this, clear CTRL2_OUTSTANDING_REQS bits before setting its value. Signed-off-by:
Robert Chiras <robert.chiras@nxp.com>
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Robert Chiras authored
Currently, the enable of the axi clock return status is ignored, causing issues when the enable fails then we try to disable it. Therefore, it is better to check the return status and disable it only when enable succeeded. Also, remove the helper functions around clk_axi, since we can directly use the clk API function for enable/disable the clock. Those functions are already checking for NULL clk and returning 0 if that's the case. Signed-off-by:
Robert Chiras <robert.chiras@nxp.com> Acked-by:
Leonard Crestez <leonard.crestez@nxp.com>
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Robert Chiras authored
The eLCDIF controller has control pin for the external LCD reset pin. Add support for it and assert this pin in enable and de-assert it in disable. Signed-off-by:
Robert Chiras <robert.chiras@nxp.com>
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Robert Chiras authored
Add new optional property 'max-memory-bandwidth', to limit the maximum bandwidth used by the MXSFB_DRM driver. Signed-off-by:
Robert Chiras <robert.chiras@nxp.com>
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Robert Chiras authored
Because of stability issues, we may want to limit the maximum bandwidth required by the MXSFB (eLCDIF) driver. Signed-off-by:
Robert Chiras <robert.chiras@nxp.com>
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Mirela Rabulea authored
Add mxsfb_atomic_helper_check to signal mode changed when bpp changed. This will trigger the execution of disable/enable on a modeset with different bpp than the current one. Signed-off-by:
Mirela Rabulea <mirela.rabulea@nxp.com> Signed-off-by:
Robert Chiras <robert.chiras@nxp.com>
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Robert Chiras authored
Currently, the vblank support is not correctly implemented in MXSFB_DRM driver. The call to drm_vblank_init is made with mode_config.num_crtc which at that time is 0. Because of this, vblank is not activated, so there won't be any vblank event submitted. For example, when running modetest with the '-v' parameter will result in an astronomical refresh rate (10000+ Hz), because of that. Signed-off-by:
Robert Chiras <robert.chiras@nxp.com>
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Robert Chiras authored
Since version 4 of eLCDIF, there are some registers that can do transformations on the input data, like re-arranging the pixel components. By doing that, we can support more pixel formats. This patch adds support for X/ABGR and RGBX/A. Although, the local alpha is not supported by eLCDIF, the alpha pixel formats were added to the supported pixel formats but it will be ignored. This was necessary since there are systems (like Android) that requires such pixel formats. Also, add support for the following pixel formats: 16 bpp: RG16 ,BG16, XR15, XB15, AR15, AB15 Set the bus format based on input from the user and panel capabilities. Save the bus format in crtc->mode.private_flags, so the bridge can use it. Signed-off-by:
Robert Chiras <robert.chiras@nxp.com> Signed-off-by:
Mirela Rabulea <mirela.rabulea@nxp.com>
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Robert Chiras authored
Use BIT(x) and GEN_MASK(h, l) for better representation the inside of various registers. Signed-off-by:
Robert Chiras <robert.chiras@nxp.com>
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Robert Chiras authored
Some of the registers, like LCDC_CTRL, CTRL2_OUTSTANDING_REQS and CTRL1_RECOVERY_ON_UNDERFLOW needs to be properly cleared/initialized for a better start and stop routine. Signed-off-by:
Robert Chiras <robert.chiras@nxp.com>
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Robert Chiras authored
Some of the existing registers in this controller are not defined, but also not used. Add them to the register definitions, so that they can be easily used in future improvements or fixes. Signed-off-by:
Robert Chiras <robert.chiras@nxp.com>
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Guido Gunther authored
Signed-off-by:
Guido Günther <guido.gunther@puri.sm>
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Guido Gunther authored
Signed-off-by:
Guido Günther <guido.gunther@puri.sm>
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Guido Gunther authored
This changes the clock tree from to osc_25m 10 12 0 25000000 0 0 50000 video_pll1_ref_sel 1 1 0 25000000 0 0 50000 video_pll1_ref_div 1 1 0 5000000 0 0 50000 video_pll1 1 1 0 593999998 0 0 50000 video_pll1_bypass 1 1 0 593999998 0 0 50000 video_pll1_out 2 2 0 593999998 0 0 50000 dsi_phy_ref 1 1 0 23760000 0 0 50000 Signed-off-by:
Guido Günther <agx@sigxcpu.org>
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Guido Gunther authored
This enables the panel to turn the backlight on and off. Signed-off-by:
Guido Günther <guido.gunther@puri.sm>
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Guido Gunther authored
Enable LCD panel output by adding nodes for the NWL DSI host controller, the Rocktech panel and the eLCDIF display controller. Signed-off-by:
Guido Günther <agx@sigxcpu.org>
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