Commit 36c9366e authored by Vitaly Wool's avatar Vitaly Wool Committed by Linus Torvalds

[PATCH] fbdev: Add framebuffer and display update module support for pnx4008

Add support for Display Update Module and RGB framebuffer device on Philips
PNX4008 ARM board.
Signed-off-by: default avatarGrigory Tolstolytkin <gtolstolytkin@ru.mvista.com>
Signed-off-by: default avatarVitaly Wool <vitalywool@gmail.com>
Signed-off-by: default avatarAntonino Daplas <adaplas@pol.net>
Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent 8320204a
......@@ -1557,6 +1557,21 @@ config FB_S3C2410_DEBUG
Turn on debugging messages. Note that you can set/unset at run time
through sysfs
config FB_PNX4008_DUM
tristate "Display Update Module support on Philips PNX4008 board"
depends on FB && ARCH_PNX4008
---help---
Say Y here to enable support for PNX4008 Display Update Module (DUM)
config FB_PNX4008_DUM_RGB
tristate "RGB Framebuffer support on Philips PNX4008 board"
depends on FB_PNX4008_DUM
select FB_CFB_FILLRECT
select FB_CFB_COPYAREA
select FB_CFB_IMAGEBLIT
---help---
Say Y here to enable support for PNX4008 RGB Framebuffer
config FB_VIRTUAL
tristate "Virtual Frame Buffer support (ONLY FOR TESTING!)"
depends on FB
......
......@@ -94,6 +94,8 @@ obj-$(CONFIG_FB_TX3912) += tx3912fb.o
obj-$(CONFIG_FB_S1D13XXX) += s1d13xxxfb.o
obj-$(CONFIG_FB_IMX) += imxfb.o
obj-$(CONFIG_FB_S3C2410) += s3c2410fb.o
obj-$(CONFIG_FB_PNX4008_DUM) += pnx4008/
obj-$(CONFIG_FB_PNX4008_DUM_RGB) += pnx4008/
# Platform or fallback drivers go here
obj-$(CONFIG_FB_VESA) += vesafb.o
......
#
# Makefile for the new PNX4008 framebuffer device driver
#
obj-$(CONFIG_FB_PNX4008_DUM) += sdum.o
obj-$(CONFIG_FB_PNX4008_DUM_RGB) += pnxrgbfb.o
/*
* linux/drivers/video/pnx4008/dum.h
*
* Internal header for SDUM
*
* 2005 (c) Koninklijke Philips N.V. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#ifndef __PNX008_DUM_H__
#define __PNX008_DUM_H__
#include <asm/arch/platform.h>
#define PNX4008_DUMCONF_VA_BASE IO_ADDRESS(PNX4008_DUMCONF_BASE)
#define PNX4008_DUM_MAIN_VA_BASE IO_ADDRESS(PNX4008_DUM_MAINCFG_BASE)
/* DUM CFG ADDRESSES */
#define DUM_CH_BASE_ADR (PNX4008_DUMCONF_VA_BASE + 0x00)
#define DUM_CH_MIN_ADR (PNX4008_DUMCONF_VA_BASE + 0x00)
#define DUM_CH_MAX_ADR (PNX4008_DUMCONF_VA_BASE + 0x04)
#define DUM_CH_CONF_ADR (PNX4008_DUMCONF_VA_BASE + 0x08)
#define DUM_CH_STAT_ADR (PNX4008_DUMCONF_VA_BASE + 0x0C)
#define DUM_CH_CTRL_ADR (PNX4008_DUMCONF_VA_BASE + 0x10)
#define CH_MARG (0x100 / sizeof(u32))
#define DUM_CH_MIN(i) (*((volatile u32 *)DUM_CH_MIN_ADR + (i) * CH_MARG))
#define DUM_CH_MAX(i) (*((volatile u32 *)DUM_CH_MAX_ADR + (i) * CH_MARG))
#define DUM_CH_CONF(i) (*((volatile u32 *)DUM_CH_CONF_ADR + (i) * CH_MARG))
#define DUM_CH_STAT(i) (*((volatile u32 *)DUM_CH_STAT_ADR + (i) * CH_MARG))
#define DUM_CH_CTRL(i) (*((volatile u32 *)DUM_CH_CTRL_ADR + (i) * CH_MARG))
#define DUM_CONF_ADR (PNX4008_DUM_MAIN_VA_BASE + 0x00)
#define DUM_CTRL_ADR (PNX4008_DUM_MAIN_VA_BASE + 0x04)
#define DUM_STAT_ADR (PNX4008_DUM_MAIN_VA_BASE + 0x08)
#define DUM_DECODE_ADR (PNX4008_DUM_MAIN_VA_BASE + 0x0C)
#define DUM_COM_BASE_ADR (PNX4008_DUM_MAIN_VA_BASE + 0x10)
#define DUM_SYNC_C_ADR (PNX4008_DUM_MAIN_VA_BASE + 0x14)
#define DUM_CLK_DIV_ADR (PNX4008_DUM_MAIN_VA_BASE + 0x18)
#define DUM_DIRTY_LOW_ADR (PNX4008_DUM_MAIN_VA_BASE + 0x20)
#define DUM_DIRTY_HIGH_ADR (PNX4008_DUM_MAIN_VA_BASE + 0x24)
#define DUM_FORMAT_ADR (PNX4008_DUM_MAIN_VA_BASE + 0x28)
#define DUM_WTCFG1_ADR (PNX4008_DUM_MAIN_VA_BASE + 0x30)
#define DUM_RTCFG1_ADR (PNX4008_DUM_MAIN_VA_BASE + 0x34)
#define DUM_WTCFG2_ADR (PNX4008_DUM_MAIN_VA_BASE + 0x38)
#define DUM_RTCFG2_ADR (PNX4008_DUM_MAIN_VA_BASE + 0x3C)
#define DUM_TCFG_ADR (PNX4008_DUM_MAIN_VA_BASE + 0x40)
#define DUM_OUTP_FORMAT1_ADR (PNX4008_DUM_MAIN_VA_BASE + 0x44)
#define DUM_OUTP_FORMAT2_ADR (PNX4008_DUM_MAIN_VA_BASE + 0x48)
#define DUM_SYNC_MODE_ADR (PNX4008_DUM_MAIN_VA_BASE + 0x4C)
#define DUM_SYNC_OUT_C_ADR (PNX4008_DUM_MAIN_VA_BASE + 0x50)
#define DUM_CONF (*(volatile u32 *)(DUM_CONF_ADR))
#define DUM_CTRL (*(volatile u32 *)(DUM_CTRL_ADR))
#define DUM_STAT (*(volatile u32 *)(DUM_STAT_ADR))
#define DUM_DECODE (*(volatile u32 *)(DUM_DECODE_ADR))
#define DUM_COM_BASE (*(volatile u32 *)(DUM_COM_BASE_ADR))
#define DUM_SYNC_C (*(volatile u32 *)(DUM_SYNC_C_ADR))
#define DUM_CLK_DIV (*(volatile u32 *)(DUM_CLK_DIV_ADR))
#define DUM_DIRTY_LOW (*(volatile u32 *)(DUM_DIRTY_LOW_ADR))
#define DUM_DIRTY_HIGH (*(volatile u32 *)(DUM_DIRTY_HIGH_ADR))
#define DUM_FORMAT (*(volatile u32 *)(DUM_FORMAT_ADR))
#define DUM_WTCFG1 (*(volatile u32 *)(DUM_WTCFG1_ADR))
#define DUM_RTCFG1 (*(volatile u32 *)(DUM_RTCFG1_ADR))
#define DUM_WTCFG2 (*(volatile u32 *)(DUM_WTCFG2_ADR))
#define DUM_RTCFG2 (*(volatile u32 *)(DUM_RTCFG2_ADR))
#define DUM_TCFG (*(volatile u32 *)(DUM_TCFG_ADR))
#define DUM_OUTP_FORMAT1 (*(volatile u32 *)(DUM_OUTP_FORMAT1_ADR))
#define DUM_OUTP_FORMAT2 (*(volatile u32 *)(DUM_OUTP_FORMAT2_ADR))
#define DUM_SYNC_MODE (*(volatile u32 *)(DUM_SYNC_MODE_ADR))
#define DUM_SYNC_OUT_C (*(volatile u32 *)(DUM_SYNC_OUT_C_ADR))
/* DUM SLAVE ADDRESSES */
#define DUM_SLAVE_WRITE_ADR (PNX4008_DUM_MAINCFG_BASE + 0x0000000)
#define DUM_SLAVE_READ1_I_ADR (PNX4008_DUM_MAINCFG_BASE + 0x1000000)
#define DUM_SLAVE_READ1_R_ADR (PNX4008_DUM_MAINCFG_BASE + 0x1000004)
#define DUM_SLAVE_READ2_I_ADR (PNX4008_DUM_MAINCFG_BASE + 0x1000008)
#define DUM_SLAVE_READ2_R_ADR (PNX4008_DUM_MAINCFG_BASE + 0x100000C)
#define DUM_SLAVE_WRITE_W ((volatile u32 *)(DUM_SLAVE_WRITE_ADR))
#define DUM_SLAVE_WRITE_HW ((volatile u16 *)(DUM_SLAVE_WRITE_ADR))
#define DUM_SLAVE_READ1_I ((volatile u8 *)(DUM_SLAVE_READ1_I_ADR))
#define DUM_SLAVE_READ1_R ((volatile u16 *)(DUM_SLAVE_READ1_R_ADR))
#define DUM_SLAVE_READ2_I ((volatile u8 *)(DUM_SLAVE_READ2_I_ADR))
#define DUM_SLAVE_READ2_R ((volatile u16 *)(DUM_SLAVE_READ2_R_ADR))
/* Sony display register addresses */
#define DISP_0_REG (0x00)
#define DISP_1_REG (0x01)
#define DISP_CAL_REG (0x20)
#define DISP_ID_REG (0x2A)
#define DISP_XMIN_L_REG (0x30)
#define DISP_XMIN_H_REG (0x31)
#define DISP_YMIN_REG (0x32)
#define DISP_XMAX_L_REG (0x34)
#define DISP_XMAX_H_REG (0x35)
#define DISP_YMAX_REG (0x36)
#define DISP_SYNC_EN_REG (0x38)
#define DISP_SYNC_RISE_L_REG (0x3C)
#define DISP_SYNC_RISE_H_REG (0x3D)
#define DISP_SYNC_FALL_L_REG (0x3E)
#define DISP_SYNC_FALL_H_REG (0x3F)
#define DISP_PIXEL_REG (0x0B)
#define DISP_DUMMY1_REG (0x28)
#define DISP_DUMMY2_REG (0x29)
#define DISP_TIMING_REG (0x98)
#define DISP_DUMP_REG (0x99)
/* Sony display constants */
#define SONY_ID1 (0x22)
#define SONY_ID2 (0x23)
/* Philips display register addresses */
#define PH_DISP_ORIENT_REG (0x003)
#define PH_DISP_YPOINT_REG (0x200)
#define PH_DISP_XPOINT_REG (0x201)
#define PH_DISP_PIXEL_REG (0x202)
#define PH_DISP_YMIN_REG (0x406)
#define PH_DISP_YMAX_REG (0x407)
#define PH_DISP_XMIN_REG (0x408)
#define PH_DISP_XMAX_REG (0x409)
/* Misc constants */
#define NO_VALID_DISPLAY_FOUND (0)
#define DISPLAY2_IS_NOT_CONNECTED (0)
/* register values */
#define V_BAC_ENABLE (BIT(0))
#define V_BAC_DISABLE_IDLE (BIT(1))
#define V_BAC_DISABLE_TRIG (BIT(2))
#define V_DUM_RESET (BIT(3))
#define V_MUX_RESET (BIT(4))
#define BAC_ENABLED (BIT(0))
#define BAC_DISABLED 0
/* Sony LCD commands */
#define V_LCD_STANDBY_OFF ((BIT(25)) | (0 << 16) | DISP_0_REG)
#define V_LCD_USE_9BIT_BUS ((BIT(25)) | (2 << 16) | DISP_1_REG)
#define V_LCD_SYNC_RISE_L ((BIT(25)) | (0 << 16) | DISP_SYNC_RISE_L_REG)
#define V_LCD_SYNC_RISE_H ((BIT(25)) | (0 << 16) | DISP_SYNC_RISE_H_REG)
#define V_LCD_SYNC_FALL_L ((BIT(25)) | (160 << 16) | DISP_SYNC_FALL_L_REG)
#define V_LCD_SYNC_FALL_H ((BIT(25)) | (0 << 16) | DISP_SYNC_FALL_H_REG)
#define V_LCD_SYNC_ENABLE ((BIT(25)) | (128 << 16) | DISP_SYNC_EN_REG)
#define V_LCD_DISPLAY_ON ((BIT(25)) | (64 << 16) | DISP_0_REG)
enum {
PAD_NONE,
PAD_512,
PAD_1024
};
enum {
RGB888,
RGB666,
RGB565,
BGR565,
ARGB1555,
ABGR1555,
ARGB4444,
ABGR4444
};
struct dum_setup {
int sync_neg_edge;
int round_robin;
int mux_int;
int synced_dirty_flag_int;
int dirty_flag_int;
int error_int;
int pf_empty_int;
int sf_empty_int;
int bac_dis_int;
u32 dirty_base_adr;
u32 command_base_adr;
u32 sync_clk_div;
int sync_output;
u32 sync_restart_val;
u32 set_sync_high;
u32 set_sync_low;
};
struct dum_ch_setup {
int disp_no;
u32 xmin;
u32 ymin;
u32 xmax;
u32 ymax;
int xmirror;
int ymirror;
int rotate;
u32 minadr;
u32 maxadr;
u32 dirtybuffer;
int pad;
int format;
int hwdirty;
int slave_trans;
};
struct disp_window {
u32 xmin_l;
u32 xmin_h;
u32 ymin;
u32 xmax_l;
u32 xmax_h;
u32 ymax;
};
#endif /* #ifndef __PNX008_DUM_H__ */
/*
* Copyright (C) 2005 Philips Semiconductors
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
* Boston, MA 02111-1307, USA, or http://www.gnu.org/licenses/gpl.html
*/
#define QCIF_W (176)
#define QCIF_H (144)
#define CIF_W (352)
#define CIF_H (288)
#define LCD_X_RES 208
#define LCD_Y_RES 320
#define LCD_X_PAD 256
#define LCD_BBP 4 /* Bytes Per Pixel */
#define DISP_MAX_X_SIZE (320)
#define DISP_MAX_Y_SIZE (208)
#define RETURNVAL_BASE (0x400)
enum fb_ioctl_returntype {
ENORESOURCESLEFT = RETURNVAL_BASE,
ERESOURCESNOTFREED,
EPROCNOTOWNER,
EFBNOTOWNER,
ECOPYFAILED,
EIOREMAPFAILED,
};
/*
* drivers/video/pnx4008/pnxrgbfb.c
*
* PNX4008's framebuffer support
*
* Author: Grigory Tolstolytkin <gtolstolytkin@ru.mvista.com>
* Based on Philips Semiconductors's code
*
* Copyrght (c) 2005 MontaVista Software, Inc.
* Copyright (c) 2005 Philips Semiconductors
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/vmalloc.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <asm/uaccess.h>
#include "sdum.h"
#include "fbcommon.h"
static u32 colreg[16];
static struct fb_var_screeninfo rgbfb_var __initdata = {
.xres = LCD_X_RES,
.yres = LCD_Y_RES,
.xres_virtual = LCD_X_RES,
.yres_virtual = LCD_Y_RES,
.bits_per_pixel = 32,
.red.offset = 16,
.red.length = 8,
.green.offset = 8,
.green.length = 8,
.blue.offset = 0,
.blue.length = 8,
.left_margin = 0,
.right_margin = 0,
.upper_margin = 0,
.lower_margin = 0,
.vmode = FB_VMODE_NONINTERLACED,
};
static struct fb_fix_screeninfo rgbfb_fix __initdata = {
.id = "RGBFB",
.line_length = LCD_X_RES * LCD_BBP,
.type = FB_TYPE_PACKED_PIXELS,
.visual = FB_VISUAL_TRUECOLOR,
.xpanstep = 0,
.ypanstep = 0,
.ywrapstep = 0,
.accel = FB_ACCEL_NONE,
};
static int channel_owned;
static int no_cursor(struct fb_info *info, struct fb_cursor *cursor)
{
return 0;
}
static int rgbfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
u_int transp, struct fb_info *info)
{
if (regno > 15)
return 1;
colreg[regno] = ((red & 0xff00) << 8) | (green & 0xff00) |
((blue & 0xff00) >> 8);
return 0;
}
static int rgbfb_mmap(struct fb_info *info, struct vm_area_struct *vma)
{
return pnx4008_sdum_mmap(info, vma, NULL);
}
static struct fb_ops rgbfb_ops = {
.fb_mmap = rgbfb_mmap,
.fb_setcolreg = rgbfb_setcolreg,
.fb_fillrect = cfb_fillrect,
.fb_copyarea = cfb_copyarea,
.fb_imageblit = cfb_imageblit,
};
static int rgbfb_remove(struct platform_device *pdev)
{
struct fb_info *info = platform_get_drvdata(pdev);
if (info) {
unregister_framebuffer(info);
fb_dealloc_cmap(&info->cmap);
framebuffer_release(info);
platform_set_drvdata(pdev, NULL);
kfree(info);
}
pnx4008_free_dum_channel(channel_owned, pdev->id);
pnx4008_set_dum_exit_notification(pdev->id);
return 0;
}
static int __devinit rgbfb_probe(struct platform_device *pdev)
{
struct fb_info *info;
struct dumchannel_uf chan_uf;
int ret;
char *option;
info = framebuffer_alloc(sizeof(u32) * 16, &pdev->dev);
if (!info) {
ret = -ENOMEM;
goto err;
}
pnx4008_get_fb_addresses(FB_TYPE_RGB, (void **)&info->screen_base,
(dma_addr_t *) &rgbfb_fix.smem_start,
&rgbfb_fix.smem_len);
if ((ret = pnx4008_alloc_dum_channel(pdev->id)) < 0)
goto err0;
else {
channel_owned = ret;
chan_uf.channelnr = channel_owned;
chan_uf.dirty = (u32 *) NULL;
chan_uf.source = (u32 *) rgbfb_fix.smem_start;
chan_uf.x_offset = 0;
chan_uf.y_offset = 0;
chan_uf.width = LCD_X_RES;
chan_uf.height = LCD_Y_RES;
if ((ret = pnx4008_put_dum_channel_uf(chan_uf, pdev->id))< 0)
goto err1;
if ((ret =
pnx4008_set_dum_channel_sync(channel_owned, CONF_SYNC_ON,
pdev->id)) < 0)
goto err1;
if ((ret =
pnx4008_set_dum_channel_dirty_detect(channel_owned,
CONF_DIRTYDETECTION_ON,
pdev->id)) < 0)
goto err1;
}
if (!fb_get_options("pnxrgbfb", &option) && !strcmp(option, "nocursor"))
rgbfb_ops.fb_cursor = no_cursor;
info->node = -1;
info->flags = FBINFO_FLAG_DEFAULT;
info->fbops = &rgbfb_ops;
info->fix = rgbfb_fix;
info->var = rgbfb_var;
info->screen_size = rgbfb_fix.smem_len;
info->pseudo_palette = info->par;
info->par = NULL;
ret = fb_alloc_cmap(&info->cmap, 256, 0);
if (ret < 0)
goto err2;
ret = register_framebuffer(info);
if (ret < 0)
goto err3;
platform_set_drvdata(pdev, info);
return 0;
err3:
fb_dealloc_cmap(&info->cmap);
err2:
framebuffer_release(info);
err1:
pnx4008_free_dum_channel(channel_owned, pdev->id);
err0:
kfree(info);
err:
return ret;
}
static struct platform_driver rgbfb_driver = {
.driver = {
.name = "rgbfb",
},
.probe = rgbfb_probe,
.remove = rgbfb_remove,
};
static int __init rgbfb_init(void)
{
return platform_driver_register(&rgbfb_driver);
}
static void __exit rgbfb_exit(void)
{
platform_driver_unregister(&rgbfb_driver);
}
module_init(rgbfb_init);
module_exit(rgbfb_exit);
MODULE_LICENSE("GPL");
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/*
* Copyright (C) 2005 Philips Semiconductors
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
* Boston, MA 02111-1307, USA, or http://www.gnu.org/licenses/gpl.html
*/
#define MAX_DUM_CHANNELS 64
#define RGB_MEM_WINDOW(x) (0x10000000 + (x)*0x00100000)
#define QCIF_OFFSET(x) (((x) == 0) ? 0x00000: ((x) == 1) ? 0x30000: -1)
#define CIF_OFFSET(x) (((x) == 0) ? 0x00000: ((x) == 1) ? 0x60000: -1)
#define CTRL_SETDIRTY (0x00000001)
#define CONF_DIRTYENABLE (0x00000020)
#define CONF_SYNCENABLE (0x00000004)
#define DIRTY_ENABLED(conf) ((conf) & 0x0020)
#define SYNC_ENABLED(conf) ((conf) & 0x0004)
/* Display 1 & 2 Write Timing Configuration */
#define PNX4008_DUM_WT_CFG 0x00372000
/* Display 1 & 2 Read Timing Configuration */
#define PNX4008_DUM_RT_CFG 0x00003A47
/* DUM Transit State Timing Configuration */
#define PNX4008_DUM_T_CFG 0x1D /* 29 HCLK cycles */
/* DUM Sync count clock divider */
#define PNX4008_DUM_CLK_DIV 0x02DD
/* Memory size for framebuffer, allocated through dma_alloc_writecombine().
* Must be PAGE aligned
*/
#define FB_DMA_SIZE (PAGE_ALIGN(SZ_1M + PAGE_SIZE))
#define OFFSET_RGBBUFFER (0xB0000)
#define OFFSET_YUVBUFFER (0x00000)
#define YUVBUFFER (lcd_video_start + OFFSET_YUVBUFFER)
#define RGBBUFFER (lcd_video_start + OFFSET_RGBBUFFER)
#define CMDSTRING_BASEADDR (0x00C000) /* iram */
#define BYTES_PER_CMDSTRING (0x80)
#define NR_OF_CMDSTRINGS (64)
#define MAX_NR_PRESTRINGS (0x40)
#define MAX_NR_POSTSTRINGS (0x40)
/* various mask definitions */
#define DUM_CLK_ENABLE 0x01
#define DUM_CLK_DISABLE 0
#define DUM_DECODE_MASK 0x1FFFFFFF
#define DUM_CHANNEL_CFG_MASK 0x01FF
#define DUM_CHANNEL_CFG_SYNC_MASK 0xFFFE00FF
#define DUM_CHANNEL_CFG_SYNC_MASK_SET 0x0CA00
#define SDUM_RETURNVAL_BASE (0x500)
#define CONF_SYNC_OFF (0x602)
#define CONF_SYNC_ON (0x603)
#define CONF_DIRTYDETECTION_OFF (0x600)
#define CONF_DIRTYDETECTION_ON (0x601)
/* Set the corresponding bit. */
#define BIT(n) (0x1U << (n))
struct dumchannel_uf {
int channelnr;
u32 *dirty;
u32 *source;
u32 x_offset;
u32 y_offset;
u32 width;
u32 height;
};
enum {
FB_TYPE_YUV,
FB_TYPE_RGB
};
struct cmdstring {
int channelnr;
uint16_t prestringlen;
uint16_t poststringlen;
uint16_t format;
uint16_t reserved;
uint16_t startaddr_low;
uint16_t startaddr_high;
uint16_t pixdatlen_low;
uint16_t pixdatlen_high;
u32 precmd[MAX_NR_PRESTRINGS];
u32 postcmd[MAX_NR_POSTSTRINGS];
};
struct dumchannel {
int channelnr;
int dum_ch_min;
int dum_ch_max;
int dum_ch_conf;
int dum_ch_stat;
int dum_ch_ctrl;
};
int pnx4008_alloc_dum_channel(int dev_id);
int pnx4008_free_dum_channel(int channr, int dev_id);
int pnx4008_get_dum_channel_uf(struct dumchannel_uf *pChan_uf, int dev_id);
int pnx4008_put_dum_channel_uf(struct dumchannel_uf chan_uf, int dev_id);
int pnx4008_set_dum_channel_sync(int channr, int val, int dev_id);
int pnx4008_set_dum_channel_dirty_detect(int channr, int val, int dev_id);
int pnx4008_force_dum_update_channel(int channr, int dev_id);
int pnx4008_get_dum_channel_config(int channr, int dev_id);
int pnx4008_sdum_mmap(struct fb_info *info, struct vm_area_struct *vma, struct device *dev);
int pnx4008_set_dum_exit_notification(int dev_id);
int pnx4008_get_fb_addresses(int fb_type, void **virt_addr,
dma_addr_t * phys_addr, int *fb_length);
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