Commit 54cebc68 authored by Linus Torvalds's avatar Linus Torvalds

Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cooloney/blackfin-2.6

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cooloney/blackfin-2.6: (60 commits)
  Blackfin arch: make sure we include the fix for SPORT hysteresis when reprogramming clocks
  Blackfin arch: Fix bogus str_ident check in gpio code
  Blackfin arch: AD7879 Touchscreen driver
  Blackfin arch: introducing bfin_addr_dcachable
  Blackfin arch: fix a typo in comments
  Blackfin arch: Remove useless head file
  Blackfin arch: make sure L2 start and length are always defined (fixes building on BF542)
  Blackfin arch: use the Blackfin on-chip ROM to do software reset when possible
  Blackfin arch: update anomaly headers to match the latest sheet
  Blackfin arch: bfin_reset() is an internal reboot function ... everyone should go through machine_restart()
  Blackfin arch: print out error/warning if you are running on the incorrect CPU type
  Blackfin arch: remove non-bf54x ifdef logic since this file is only compiled on bf54x parts
  Blackfin arch: update board defconfigs
  Blackfin arch: Add optional verbose debug
  Blackfin arch: emulate a TTY over the EMUDAT/JTAG interface
  Blackfin arch: have is_user_addr_valid() check for overflows (like when address is -1)
  Blackfin arch: ptrace - fix off-by-one check on end of memory regions
  Blackfin arch: Enable framebuffer support for the BF526-EZkit TFT LCD display
  Blackfin arch: flash memory map and dm9000 resources updating
  Blackfin arch: early prink code still use uart core console functions to parse and set configure option string
  ...
parents fffdedef 71de1f8a
A Simple Guide to Configure KGDB
Sonic Zhang <sonic.zhang@analog.com>
Aug. 24th 2006
This KGDB patch enables the kernel developer to do source level debugging on
the kernel for the Blackfin architecture. The debugging works over either the
ethernet interface or one of the uarts. Both software breakpoints and
hardware breakpoints are supported in this version.
http://docs.blackfin.uclinux.org/doku.php?id=kgdb
2 known issues:
1. This bug:
http://blackfin.uclinux.org/tracker/index.php?func=detail&aid=544&group_id=18&atid=145
The GDB client for Blackfin uClinux causes incorrect values of local
variables to be displayed when the user breaks the running of kernel in GDB.
2. Because of a hardware bug in Blackfin 533 v1.0.3:
05000067 - Watchpoints (Hardware Breakpoints) are not supported
Hardware breakpoints cannot be set properly.
Debug over Ethernet:
1. Compile and install the cross platform version of gdb for blackfin, which
can be found at $(BINROOT)/bfin-elf-gdb.
2. Apply this patch to the 2.6.x kernel. Select the menuconfig option under
"Kernel hacking" -> "Kernel debugging" -> "KGDB: kernel debug with remote gdb".
With this selected, option "Full Symbolic/Source Debugging support" and
"Compile the kernel with frame pointers" are also selected.
3. Select option "KGDB: connect over (Ethernet)". Add "kgdboe=@target-IP/,@host-IP/" to
the option "Compiled-in Kernel Boot Parameter" under "Kernel hacking".
4. Connect minicom to the serial port and boot the kernel image.
5. Configure the IP "/> ifconfig eth0 target-IP"
6. Start GDB client "bfin-elf-gdb vmlinux".
7. Connect to the target "(gdb) target remote udp:target-IP:6443".
8. Set software breakpoint "(gdb) break sys_open".
9. Continue "(gdb) c".
10. Run ls in the target console "/> ls".
11. Breakpoint hits. "Breakpoint 1: sys_open(..."
12. Display local variables and function paramters.
(*) This operation gives wrong results, see known issue 1.
13. Single stepping "(gdb) si".
14. Remove breakpoint 1. "(gdb) del 1"
15. Set hardware breakpoint "(gdb) hbreak sys_open".
16. Continue "(gdb) c".
17. Run ls in the target console "/> ls".
18. Hardware breakpoint hits. "Breakpoint 1: sys_open(...".
(*) This hardware breakpoint will not be hit, see known issue 2.
19. Continue "(gdb) c".
20. Interrupt the target in GDB "Ctrl+C".
21. Detach from the target "(gdb) detach".
22. Exit GDB "(gdb) quit".
Debug over the UART:
1. Compile and install the cross platform version of gdb for blackfin, which
can be found at $(BINROOT)/bfin-elf-gdb.
2. Apply this patch to the 2.6.x kernel. Select the menuconfig option under
"Kernel hacking" -> "Kernel debugging" -> "KGDB: kernel debug with remote gdb".
With this selected, option "Full Symbolic/Source Debugging support" and
"Compile the kernel with frame pointers" are also selected.
3. Select option "KGDB: connect over (UART)". Set "KGDB: UART port number" to be
a different one from the console. Don't forget to change the mode of
blackfin serial driver to PIO. Otherwise kgdb works incorrectly on UART.
4. If you want connect to kgdb when the kernel boots, enable
"KGDB: Wait for gdb connection early"
5. Compile kernel.
6. Connect minicom to the serial port of the console and boot the kernel image.
7. Start GDB client "bfin-elf-gdb vmlinux".
8. Set the baud rate in GDB "(gdb) set remotebaud 57600".
9. Connect to the target on the second serial port "(gdb) target remote /dev/ttyS1".
10. Set software breakpoint "(gdb) break sys_open".
11. Continue "(gdb) c".
12. Run ls in the target console "/> ls".
13. A breakpoint is hit. "Breakpoint 1: sys_open(..."
14. All other operations are the same as that in KGDB over Ethernet.
Debug over the same UART as console:
1. Compile and install the cross platform version of gdb for blackfin, which
can be found at $(BINROOT)/bfin-elf-gdb.
2. Apply this patch to the 2.6.x kernel. Select the menuconfig option under
"Kernel hacking" -> "Kernel debugging" -> "KGDB: kernel debug with remote gdb".
With this selected, option "Full Symbolic/Source Debugging support" and
"Compile the kernel with frame pointers" are also selected.
3. Select option "KGDB: connect over UART". Set "KGDB: UART port number" to console.
Don't forget to change the mode of blackfin serial driver to PIO.
Otherwise kgdb works incorrectly on UART.
4. If you want connect to kgdb when the kernel boots, enable
"KGDB: Wait for gdb connection early"
5. Connect minicom to the serial port and boot the kernel image.
6. (Optional) Ask target to wait for gdb connection by entering Ctrl+A. In minicom, you should enter Ctrl+A+A.
7. Start GDB client "bfin-elf-gdb vmlinux".
8. Set the baud rate in GDB "(gdb) set remotebaud 57600".
9. Connect to the target "(gdb) target remote /dev/ttyS0".
10. Set software breakpoint "(gdb) break sys_open".
11. Continue "(gdb) c". Then enter Ctrl+C twice to stop GDB connection.
12. Run ls in the target console "/> ls". Dummy string can be seen on the console.
13. Then connect the gdb to target again. "(gdb) target remote /dev/ttyS0".
Now you will find a breakpoint is hit. "Breakpoint 1: sys_open(..."
14. All other operations are the same as that in KGDB over Ethernet. The only
difference is that after continue command in GDB, please stop GDB
connection by 2 "Ctrl+C"s and connect again after breakpoints are hit or
Ctrl+A is entered.
......@@ -162,16 +162,28 @@ config BF549
config BF561
bool "BF561"
help
Not Supported Yet - Work in progress - BF561 Processor Support.
BF561 Processor Support.
endchoice
config BF_REV_MIN
int
default 0 if (BF52x || BF54x)
default 2 if (BF537 || BF536 || BF534)
default 3 if (BF561 ||BF533 || BF532 || BF531)
config BF_REV_MAX
int
default 2 if (BF52x || BF54x)
default 3 if (BF537 || BF536 || BF534)
default 5 if (BF561)
default 6 if (BF533 || BF532 || BF531)
choice
prompt "Silicon Rev"
default BF_REV_0_1 if BF527
default BF_REV_0_2 if BF537
default BF_REV_0_3 if BF533
default BF_REV_0_0 if BF549
default BF_REV_0_1 if (BF52x || BF54x)
default BF_REV_0_2 if (BF534 || BF536 || BF537)
default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF561)
config BF_REV_0_0
bool "0.0"
......@@ -183,7 +195,7 @@ config BF_REV_0_1
config BF_REV_0_2
bool "0.2"
depends on (BF537 || BF536 || BF534)
depends on (BF52x || BF537 || BF536 || BF534 || BF54x)
config BF_REV_0_3
bool "0.3"
......@@ -197,6 +209,10 @@ config BF_REV_0_5
bool "0.5"
depends on (BF561 || BF533 || BF532 || BF531)
config BF_REV_0_6
bool "0.6"
depends on (BF533 || BF532 || BF531)
config BF_REV_ANY
bool "any"
......@@ -249,7 +265,7 @@ config MEM_MT48LC8M32B2B5_7
config MEM_MT48LC32M16A2TG_75
bool
depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP)
depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD)
default y
source "arch/blackfin/mach-bf527/Kconfig"
......@@ -286,13 +302,20 @@ config BOOT_LOAD
memory region is used to capture NULL pointer references as well
as some core kernel functions.
config ROM_BASE
hex "Kernel ROM Base"
default "0x20040000"
range 0x20000000 0x20400000 if !(BF54x || BF561)
range 0x20000000 0x30000000 if (BF54x || BF561)
help
comment "Clock/PLL Setup"
config CLKIN_HZ
int "Frequency of the crystal on the board in Hz"
default "11059200" if BFIN533_STAMP
default "27000000" if BFIN533_EZKIT
default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS || BLACKSTAMP)
default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD)
default "30000000" if BFIN561_EZKIT
default "24576000" if PNAV10
default "10000000" if BFIN532_IP0X
......@@ -332,7 +355,7 @@ config VCO_MULT
default "22" if BFIN533_BLUETECHNIX_CM
default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
default "20" if BFIN561_EZKIT
default "16" if (H8606_HVSISTEMAS || BLACKSTAMP)
default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD)
help
This controls the frequency of the on-chip PLL. This can be between 1 and 64.
PLL Frequency = (Crystal Frequency) * (this setting)
......@@ -368,14 +391,6 @@ config SCLK_DIV
This can be between 1 and 15
System Clock = (PLL frequency) / (this setting)
config MAX_MEM_SIZE
int "Max SDRAM Memory Size in MBytes"
depends on !MPU
default 512
help
This is the max memory size that the kernel will create CPLB
tables for. Your system will not be able to handle any more.
choice
prompt "DDR SDRAM Chip Type"
depends on BFIN_KERNEL_CLOCK
......@@ -389,6 +404,14 @@ config MEM_MT46V32M16_5B
bool "MT46V32M16_5B"
endchoice
config MAX_MEM_SIZE
int "Max SDRAM Memory Size in MBytes"
depends on !MPU
default 512
help
This is the max memory size that the kernel will create CPLB
tables for. Your system will not be able to handle any more.
#
# Max & Min Speeds for various Chips
#
......@@ -455,8 +478,6 @@ config CYCLES_CLOCKSOURCE
source kernel/time/Kconfig
comment "Memory Setup"
comment "Misc"
choice
......@@ -622,6 +643,15 @@ config CPLB_SWITCH_TAB_L1
If enabled, the CPLB Switch Tables are linked
into L1 data memory. (less latency)
config APP_STACK_L1
bool "Support locating application stack in L1 Scratch Memory"
default y
help
If enabled the application stack can be located in L1
scratch memory (less latency).
Currently only works with FLAT binaries.
comment "Speed Optimizations"
config BFIN_INS_LOWOVERHEAD
bool "ins[bwl] low overhead, higher interrupt latency"
......@@ -755,6 +785,13 @@ config BFIN_WT
endchoice
config BFIN_L2_CACHEABLE
bool "Cache L2 SRAM"
depends on (BFIN_DCACHE || BFIN_ICACHE) && (BF54x || BF561)
default n
help
Select to make L2 SRAM cacheable in L1 data and instruction cache.
config MPU
bool "Enable the memory protection unit (EXPERIMENTAL)"
default n
......
......@@ -2,6 +2,22 @@ menu "Kernel hacking"
source "lib/Kconfig.debug"
config HAVE_ARCH_KGDB
def_bool y
config DEBUG_VERBOSE
bool "Verbose fault messages"
default y
select PRINTK
help
When a program crashes due to an exception, or the kernel detects
an internal error, the kernel can print a not so brief message
explaining what the problem was. This debugging information is
useful to developers and kernel hackers when tracking down problems,
but mostly meaningless to other people. This is always helpful for
debugging but serves no purpose on a production system.
Most people should say N here.
config DEBUG_MMRS
bool "Generate Blackfin MMR tree"
select DEBUG_FS
......@@ -22,6 +38,44 @@ config DEBUG_HWERR
hardware error interrupts and need to know where they are coming
from.
config DEBUG_DOUBLEFAULT
bool "Debug Double Faults"
default n
help
If an exception is caused while executing code within the exception
handler, the NMI handler, the reset vector, or in emulator mode,
a double fault occurs. On the Blackfin, this is a unrecoverable
event. You have two options:
- RESET exactly when double fault occurs. The excepting
instruction address is stored in RETX, where the next kernel
boot will print it out.
- Print debug message. This is much more error prone, although
easier to handle. It is error prone since:
- The excepting instruction is not committed.
- All writebacks from the instruction are prevented.
- The generated exception is not taken.
- The EXCAUSE field is updated with an unrecoverable event
The only way to check this is to see if EXCAUSE contains the
unrecoverable event value at every exception return. By selecting
this option, you are skipping over the faulting instruction, and
hoping things stay together enough to print out a debug message.
This does add a little kernel code, but is the only method to debug
double faults - if unsure say "Y"
choice
prompt "Double Fault Failure Method"
default DEBUG_DOUBLEFAULT_PRINT
depends on DEBUG_DOUBLEFAULT
config DEBUG_DOUBLEFAULT_PRINT
bool "Print"
config DEBUG_DOUBLEFAULT_RESET
bool "Reset"
endchoice
config DEBUG_ICACHE_CHECK
bool "Check Instruction cache coherency"
depends on DEBUG_KERNEL
......@@ -143,6 +197,7 @@ config DEBUG_BFIN_NO_KERN_HWTRACE
config EARLY_PRINTK
bool "Early printk"
default n
select SERIAL_CORE_CONSOLE
help
This option enables special console drivers which allow the kernel
to print messages very early in the bootup process.
......
......@@ -67,6 +67,7 @@ rev-$(CONFIG_BF_REV_0_2) := 0.2
rev-$(CONFIG_BF_REV_0_3) := 0.3
rev-$(CONFIG_BF_REV_0_4) := 0.4
rev-$(CONFIG_BF_REV_0_5) := 0.5
rev-$(CONFIG_BF_REV_0_6) := 0.6
rev-$(CONFIG_BF_REV_NONE) := none
rev-$(CONFIG_BF_REV_ANY) := any
......
This diff is collapsed.
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.22.12
# Linux kernel version: 2.6.22.14
#
# CONFIG_MMU is not set
# CONFIG_FPU is not set
......@@ -192,7 +192,7 @@ CONFIG_CLKIN_HZ=25000000
# CONFIG_BFIN_KERNEL_CLOCK is not set
CONFIG_MAX_VCO_HZ=400000000
CONFIG_MIN_VCO_HZ=50000000
CONFIG_MAX_SCLK_HZ=133000000
CONFIG_MAX_SCLK_HZ=133333333
CONFIG_MIN_SCLK_HZ=27000000
#
......@@ -516,7 +516,7 @@ CONFIG_MTD_COMPLEX_MAPPINGS=y
#
# CONFIG_MTD_DATAFLASH is not set
CONFIG_MTD_M25P80=y
CONFIG_M25PXX_USE_FAST_READ=y
# CONFIG_M25PXX_USE_FAST_READ is not set
# CONFIG_MTD_SLRAM is not set
# CONFIG_MTD_PHRAM is not set
# CONFIG_MTD_MTDRAM is not set
......@@ -635,25 +635,25 @@ CONFIG_INPUT=y
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_TSDEV is not set
CONFIG_INPUT_EVDEV=m
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_EVBUG is not set
#
# Input Device Drivers
#
# CONFIG_INPUT_KEYBOARD is not set
CONFIG_INPUT_KEYBOARD=y
# CONFIG_KEYBOARD_ATKBD is not set
# CONFIG_KEYBOARD_SUNKBD is not set
# CONFIG_KEYBOARD_LKKBD is not set
# CONFIG_KEYBOARD_XTKBD is not set
# CONFIG_KEYBOARD_NEWTON is not set
# CONFIG_KEYBOARD_STOWAWAY is not set
CONFIG_KEYBOARD_GPIO=y
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TABLET is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
CONFIG_INPUT_MISC=y
# CONFIG_INPUT_ATI_REMOTE is not set
# CONFIG_INPUT_ATI_REMOTE2 is not set
# CONFIG_INPUT_KEYSPAN_REMOTE is not set
# CONFIG_INPUT_POWERMATE is not set
# CONFIG_INPUT_YEALINK is not set
# CONFIG_INPUT_UINPUT is not set
# CONFIG_BF53X_PFBUTTONS is not set
# CONFIG_INPUT_MISC is not set
#
# Hardware I/O ports
......@@ -681,7 +681,15 @@ CONFIG_BFIN_TIMER_LATENCY=y
#
# Serial drivers
#
# CONFIG_SERIAL_8250 is not set
CONFIG_SERIAL_8250=y
# CONFIG_SERIAL_8250_CONSOLE is not set
CONFIG_SERIAL_8250_NR_UARTS=4
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
CONFIG_SERIAL_8250_EXTENDED=y
# CONFIG_SERIAL_8250_MANY_PORTS is not set
CONFIG_SERIAL_8250_SHARE_IRQ=y
# CONFIG_SERIAL_8250_DETECT_IRQ is not set
# CONFIG_SERIAL_8250_RSA is not set
#
# Non-8250 serial port support
......
......@@ -63,7 +63,6 @@ extern void bfin_dcache_init(void);
extern void init_exception_vectors(void);
extern void program_IAR(void);
extern void bfin_reset(void);
extern asmlinkage void lower_to_irq14(void);
extern asmlinkage void bfin_return_from_exception(void);
extern asmlinkage void evt14_softirq(void);
......@@ -92,6 +91,8 @@ extern int sram_free(const void*);
extern void *sram_alloc_with_lsl(size_t, unsigned long);
extern int sram_free_with_lsl(const void*);
extern void *isram_memcpy(void *dest, const void *src, size_t n);
extern const char bfin_board_name[];
extern unsigned long bfin_sic_iwr[];
......@@ -104,7 +105,7 @@ extern char _stext_l1[], _etext_l1[], _sdata_l1[], _edata_l1[], _sbss_l1[],
_stext_l2[], _etext_l2[], _sdata_l2[], _edata_l2[], _sbss_l2[],
_ebss_l2[], _l2_lma_start[];
/* only used when CONFIG_MTD_UCLINUX */
/* only used when MTD_UCLINUX */
extern unsigned long memory_mtd_start, memory_mtd_end, mtd_size;
#ifdef CONFIG_BFIN_ICACHE_LOCK
......
/* Blackfin on-chip ROM API
*
* Copyright 2008 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#ifndef __BFROM_H__
#define __BFROM_H__
#include <linux/types.h>
/* Possible syscontrol action flags */
#define SYSCTRL_READ 0x00000000 /* read registers */
#define SYSCTRL_WRITE 0x00000001 /* write registers */
#define SYSCTRL_SYSRESET 0x00000002 /* perform system reset */
#define SYSCTRL_CORERESET 0x00000004 /* perform core reset */
#define SYSCTRL_SOFTRESET 0x00000006 /* perform core and system reset */
#define SYSCTRL_VRCTL 0x00000010 /* read/write VR_CTL register */
#define SYSCTRL_EXTVOLTAGE 0x00000020 /* VDDINT supplied externally */
#define SYSCTRL_INTVOLTAGE 0x00000000 /* VDDINT generated by on-chip regulator */
#define SYSCTRL_OTPVOLTAGE 0x00000040 /* For Factory Purposes Only */
#define SYSCTRL_PLLCTL 0x00000100 /* read/write PLL_CTL register */
#define SYSCTRL_PLLDIV 0x00000200 /* read/write PLL_DIV register */
#define SYSCTRL_LOCKCNT 0x00000400 /* read/write PLL_LOCKCNT register */
#define SYSCTRL_PLLSTAT 0x00000800 /* read/write PLL_STAT register */
typedef struct ADI_SYSCTRL_VALUES {
uint16_t uwVrCtl;
uint16_t uwPllCtl;
uint16_t uwPllDiv;
uint16_t uwPllLockCnt;
uint16_t uwPllStat;
} ADI_SYSCTRL_VALUES;
static uint32_t (* const bfrom_SysControl)(uint32_t action_flags, ADI_SYSCTRL_VALUES *power_settings, void *reserved) = (void *)0xEF000038;
/* We need a dedicated function since we need to screw with the stack pointer
* when resetting. The on-chip ROM will save/restore registers on the stack
* when doing a system reset, so the stack cannot be outside of the chip.
*/
__attribute__((__noreturn__))
static inline void bfrom_SoftReset(void *new_stack)
{
while (1)
__asm__ __volatile__(
"sp = %[stack];"
"jump (%[bfrom_syscontrol]);"
: : [bfrom_syscontrol] "p"(bfrom_SysControl),
"q0"(SYSCTRL_SOFTRESET),
"q1"(0),
"q2"(NULL),
[stack] "p"(new_stack)
);
}
/* OTP Functions */
static uint32_t (* const bfrom_OtpCommand)(uint32_t command, uint32_t value) = (void *)0xEF000018;
static uint32_t (* const bfrom_OtpRead)(uint32_t page, uint32_t flags, uint64_t *page_content) = (void *)0xEF00001A;
static uint32_t (* const bfrom_OtpWrite)(uint32_t page, uint32_t flags, uint64_t *page_content) = (void *)0xEF00001C;
/* otp command: defines for "command" */
#define OTP_INIT 0x00000001
#define OTP_CLOSE 0x00000002
/* otp read/write: defines for "flags" */
#define OTP_LOWER_HALF 0x00000000 /* select upper/lower 64-bit half (bit 0) */
#define OTP_UPPER_HALF 0x00000001
#define OTP_NO_ECC 0x00000010 /* do not use ECC */
#define OTP_LOCK 0x00000020 /* sets page protection bit for page */
#define OTP_CHECK_FOR_PREV_WRITE 0x00000080
/* Return values for all functions */
#define OTP_SUCCESS 0x00000000
#define OTP_MASTER_ERROR 0x001
#define OTP_WRITE_ERROR 0x003
#define OTP_READ_ERROR 0x005
#define OTP_ACC_VIO_ERROR 0x009
#define OTP_DATA_MULT_ERROR 0x011
#define OTP_ECC_MULT_ERROR 0x021
#define OTP_PREV_WR_ERROR 0x041
#define OTP_DATA_SB_WARN 0x100
#define OTP_ECC_SB_WARN 0x200
#endif
......@@ -30,8 +30,6 @@
#ifndef _BLACKFIN_CACHEFLUSH_H
#define _BLACKFIN_CACHEFLUSH_H
#include <asm/cplb.h>
extern void blackfin_icache_dcache_flush_range(unsigned int, unsigned int);
extern void blackfin_icache_flush_range(unsigned int, unsigned int);
extern void blackfin_dcache_flush_range(unsigned int, unsigned int);
......
......@@ -55,7 +55,13 @@
#endif
#define L1_DMEMORY (CPLB_LOCK | CPLB_COMMON)
#define L2_MEMORY (CPLB_COMMON)
#ifdef CONFIG_BFIN_L2_CACHEABLE
#define L2_IMEMORY (SDRAM_IGENERIC)
#define L2_DMEMORY (SDRAM_DGENERIC)
#else
#define L2_IMEMORY (CPLB_COMMON)
#define L2_DMEMORY (CPLB_COMMON)
#endif
#define SDRAM_DNON_CHBL (CPLB_COMMON)
#define SDRAM_EBIU (CPLB_COMMON)
#define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)
......
......@@ -90,6 +90,20 @@ extern u_long dpdt_swapcount_table[];
extern unsigned long reserved_mem_dcache_on;
extern unsigned long reserved_mem_icache_on;
extern void generate_cpl_tables(void);
extern void generate_cplb_tables(void);
static inline int bfin_addr_dcachable(unsigned long addr)
{
#ifdef CONFIG_BFIN_DCACHE
if (addr < (_ramend - DMA_UNCACHED_REGION))
return 1;
#endif
if (reserved_mem_dcache_on &&
addr >= _ramend && addr < physical_mem_end)
return 1;
return 0;
}
#endif
#ifndef _ASM_BLACKFIN_CPUMASK_H
#define _ASM_BLACKFIN_CPUMASK_H
#include <asm-generic/cpumask.h>
#endif /* _ASM_BLACKFIN_CPUMASK_H */
......@@ -80,4 +80,15 @@ extern int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
extern void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
int nhwentries, enum dma_data_direction direction);
static inline void dma_sync_single_for_cpu(struct device *dev,
dma_addr_t handle, size_t size,
enum dma_data_direction dir)
{
}
static inline void dma_sync_single_for_device(struct device *dev,
dma_addr_t handle, size_t size,
enum dma_data_direction dir)
{
}
#endif /* _BLACKFIN_DMA_MAPPING_H */
......@@ -124,9 +124,16 @@ enum regnames {
/* Number of bytes of registers. */
#define NUMREGBYTES BFIN_NUM_REGS*4
#define BREAKPOINT() asm(" EXCPT 2;");
#define BREAK_INSTR_SIZE 2
#define HW_BREAKPOINT_NUM 6
static inline void arch_kgdb_breakpoint(void)
{
asm(" EXCPT 2;");
}
#define BREAK_INSTR_SIZE 2
#define CACHE_FLUSH_IS_SAFE 1
#define HW_INST_WATCHPOINT_NUM 6
#define HW_WATCHPOINT_NUM 8
#define TYPE_INST_WATCHPOINT 0
#define TYPE_DATA_WATCHPOINT 1
/* Instruction watchpoint address control register bits mask */
#define WPPWR 0x1
......@@ -163,10 +170,11 @@ enum regnames {
#define WPDAEN1 0x8
#define WPDCNTEN0 0x10
#define WPDCNTEN1 0x20
#define WPDSRC0 0xc0
#define WPDACC0 0x300
#define WPDACC0_OFFSET 8
#define WPDSRC1 0xc00
#define WPDACC1 0x3000
#define WPDACC1_OFFSET 12
/* Watchpoint status register bits mask */
#define STATIA0 0x1
......@@ -178,7 +186,4 @@ enum regnames {
#define STATDA0 0x40
#define STATDA1 0x80
extern void kgdb_print(const char *fmt, ...);
extern void init_kgdb_uart(void);
#endif
......@@ -45,49 +45,12 @@ extern unsigned long l1_stack_len;
extern int l1sram_free(const void*);
extern void *l1sram_alloc_max(void*);
static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
{
}
/* Called when creating a new context during fork() or execve(). */
static inline int
init_new_context(struct task_struct *tsk, struct mm_struct *mm)
{
#ifdef CONFIG_MPU
unsigned long p = __get_free_pages(GFP_KERNEL, page_mask_order);
mm->context.page_rwx_mask = (unsigned long *)p;
memset(mm->context.page_rwx_mask, 0,
page_mask_nelts * 3 * sizeof(long));
#endif
return 0;
}
static inline void free_l1stack(void)
{
nr_l1stack_tasks--;
if (nr_l1stack_tasks == 0)
l1sram_free(l1_stack_base);
}
static inline void destroy_context(struct mm_struct *mm)
{
struct sram_list_struct *tmp;
if (current_l1_stack_save == mm->context.l1_stack_save)
current_l1_stack_save = NULL;
if (mm->context.l1_stack_save)
free_l1stack();
while ((tmp = mm->context.sram_list)) {
mm->context.sram_list = tmp->next;