- Jan 17, 2020
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Guido Gunther authored
Signed-off-by:
Guido Günther <guido.gunther@puri.sm>
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Guido Gunther authored
This reverts commit 245595e8. mesa sets longer timeouts so renedering breaks.
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Guido Gunther authored
Signed-off-by:
Guido Günther <guido.gunther@puri.sm>
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Guido Gunther authored
Signed-off-by:
Guido Günther <guido.gunther@puri.sm>
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Guido Gunther authored
Signed-off-by:
Guido Günther <guido.gunther@puri.sm>
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Guido Gunther authored
This patch is what Emcraft's Dmitry Konyshev did in their tree. If seems to fix the phy powerup. Signed-off-by:
Guido Günther <guido.gunther@puri.sm>
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This clock is a high precision clock on imx8mq-evk board that will be used by HDMI phy. Signed-off-by:
Laurentiu Palcu <laurentiu.palcu@nxp.com>
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Guido Gunther authored
We don't care about ipuv3 on imx and this part diverges from mainline quite a bit. Signed-off-by:
Guido Günther <guido.gunther@puri.sm>
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Guido Gunther authored
Signed-off-by:
Guido Günther <guido.gunther@puri.sm>
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Guido Gunther authored
Signed-off-by:
Guido Günther <guido.gunther@puri.sm>
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Guido Gunther authored
Signed-off-by:
Guido Günther <guido.gunther@puri.sm>
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Guido Gunther authored
This eases compilation Signed-off-by:
Guido Günther <guido.gunther@puri.sm>
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Guido Gunther authored
Signed-off-by:
Guido Günther <guido.gunther@puri.sm>
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Guido Gunther authored
this gives us dp_link back This reverts commit 9a42c7c6.
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This pixel format is a fully packed and 10bits variant of NV12. A luma pixel would take 10bits in memory, without any filled bits between pixels in a stride. Signed-off-by:
Randy Li <ayaka@soulik.info> Signed-off-by:
Laurentiu Palcu <laurentiu.palcu@nxp.com>
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These formats will be used by VPU and DCSS. Signed-off-by:
Laurentiu Palcu <laurentiu.palcu@nxp.com> [ Aisheng : VENDOR_VSI changed to 0xf1 ] Signed-off-by:
Dong Aisheng <aisheng.dong@nxp.com>
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Add a new fb modifier for Vivante compressed and tiled pixle layout which can be decompressed by DEC400D module in DCSS. Signed-off-by:
Fancy Fang <chen.fang@nxp.com> Signed-off-by:
Laurentiu Palcu <laurentiu.palcu@nxp.com>
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Guido Gunther authored
Signed-off-by:
Guido Günther <guido.gunther@puri.sm>
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Guido Gunther authored
Signed-off-by:
Guido Günther <guido.gunther@puri.sm>
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Add hdmi phy video mode valid function to filter the video modes. Signed-off-by:
Sandor Yu <Sandor.yu@nxp.com> Reviewed-by:
Robby Cai <robby.cai@nxp.com>
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The HDR_OUTPUT_METADATA property is needed in order for userspace to instruct the sink to switch to HDR10 mode. Signed-off-by:
Laurentiu Palcu <laurentiu.palcu@nxp.com>
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Add dual mode support for imx8qm. imx8qm hdmi/dp driver are ready to support 4K. Signed-off-by:
Sandor Yu <Sandor.yu@nxp.com>
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Add Display Port driver support for NXP Layerscape LS1028A platform. Signed-off-by:
Wen He <wen.he_1@nxp.com>
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Add power_on of the cnds_plat_data to __cdns_dp_probe as to update Board related configuration initalization. Signed-off-by:
Wen He <wen.he_1@nxp.com>
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add struct imx_mhdp_device for imx specific. add imx8mq hdmi support. move imx8qm specific functions to plat_data uniform variable name. Signed-off-by:
Sandor Yu <Sandor.yu@nxp.com>
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This patch adds support in DCSS for Vivante tiled-compressed buffers. Signed-off-by:
Fancy Fang <chen.fang@nxp.com> Signed-off-by:
Laurentiu Palcu <laurentiu.palcu@nxp.com>
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The 27MHz external oscillator offers a high precision low jitter clock and is suitable for high pixel clocks modes(ie 4K@60). Signed-off-by:
Laurentiu Palcu <laurentiu.palcu@nxp.com>
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This adds initial support for iMX8MQ's Display Controller Subsystem (DCSS). Some of its capabilities include: * 4K@60fps; * HDR10; * one graphics and 2 video pipelines; * on-the-fly decompression of compressed video and graphics; The reference manual can be found here: https://www.nxp.com/webapp/Download?colCode=IMX8MDQLQRM The current patch adds only basic functionality: one primary plane for graphics, linear, tiled and super-tiled buffers support (no graphics decompression yet), no HDR10 and no video planes. Video planes support and HDR10 will be added in subsequent patches once per-plane de-gamma/CSC/gamma support is in. Signed-off-by:
Laurentiu Palcu <laurentiu.palcu@nxp.com>
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- Jan 14, 2020
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Guido Gunther authored
This adds initial support for the NWL MIPI DSI Host controller found on i.MX8 SoCs. It adds support for the i.MX8MQ but the same IP can be found on e.g. the i.MX8QXP. It has been tested on the Librem 5 devkit using mxsfb. Signed-off-by:
Guido Günther <agx@sigxcpu.org> Co-developed-by:
Robert Chiras <robert.chiras@nxp.com> Signed-off-by:
Robert Chiras <robert.chiras@nxp.com> Tested-by:
Robert Chiras <robert.chiras@nxp.com> Tested-by:
Martin Kepplinger <martin.kepplinger@puri.sm>
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Guido Gunther authored
The Northwest Logic MIPI DSI IP core can be found in NXPs i.MX8 SoCs. Signed-off-by:
Guido Günther <agx@sigxcpu.org> Tested-by:
Robert Chiras <robert.chiras@nxp.com> Reviewed-by:
Rob Herring <robh@kernel.org>
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Guido Gunther authored
Otherwise it breaks mipi Signed-off-by:
Guido Günther <guido.gunther@puri.sm>
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Guido Gunther authored
This fixes compilation on next-20191029
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Guido Gunther authored
This reverts commit b45ce5e0.
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Guido Gunther authored
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Add the initial configuration for clocks that need default parent and rate setting. This is based on the vendor tree clock provider parents and rates configuration except this is doing the setup in dts rather then using clock consumer API in a clock provider driver. Note that by adding the initial rate setting for audio_pll1/audio_pll setting we need to remove it from imx8mq-librem5-devkit.dts imx8mq-librem5-devkit.dts Signed-off-by:
Abel Vesa <abel.vesa@nxp.com> Signed-off-by:
Daniel Baluta <daniel.baluta@nxp.com>
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Bit 21 can alter the CTRL2_OUTSTANDING_REQS value right after the eLCDIF is enabled, since it comes up with default value of 1 (this behaviour has been seen on some imx8 platforms). In order to fix this, clear CTRL2_OUTSTANDING_REQS bits before setting its value. Signed-off-by:
Robert Chiras <robert.chiras@nxp.com>
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Currently, the enable of the axi clock return status is ignored, causing issues when the enable fails then we try to disable it. Therefore, it is better to check the return status and disable it only when enable succeeded. Also, remove the helper functions around clk_axi, since we can directly use the clk API function for enable/disable the clock. Those functions are already checking for NULL clk and returning 0 if that's the case. Signed-off-by:
Robert Chiras <robert.chiras@nxp.com> Acked-by:
Leonard Crestez <leonard.crestez@nxp.com>
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The eLCDIF controller has control pin for the external LCD reset pin. Add support for it and assert this pin in enable and de-assert it in disable. Signed-off-by:
Robert Chiras <robert.chiras@nxp.com>
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Add new optional property 'max-memory-bandwidth', to limit the maximum bandwidth used by the MXSFB_DRM driver. Signed-off-by:
Robert Chiras <robert.chiras@nxp.com>
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Because of stability issues, we may want to limit the maximum bandwidth required by the MXSFB (eLCDIF) driver. Signed-off-by:
Robert Chiras <robert.chiras@nxp.com>
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