Commit d29ff59f authored by Martin Kepplinger's avatar Martin Kepplinger
parent 37791ac2
Pipeline #64845 passed with stage
in 65 minutes and 4 seconds
......@@ -1166,7 +1166,7 @@
assigned-clocks = <&clk IMX8MQ_CLK_CSI1_CORE>,
<&clk IMX8MQ_CLK_CSI1_PHY_REF>,
<&clk IMX8MQ_CLK_CSI1_ESC>;
assigned-clock-rates = <133000000>, <100000000>, <66000000>;
assigned-clock-rates = <266000000>, <150000000>, <66000000>;
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
<&clk IMX8MQ_SYS2_PLL_1000M>,
<&clk IMX8MQ_SYS1_PLL_800M>;
......
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