This reverts commit 72d7e241.

Abel Vesa authored 5 years ago and Martin Kepplinger committed 5 years ago

Allow the affinity setting to be done also in GPC. On the i.MX8MQ SoC,
due to the ERR11171, the GIC is not able to wake up the cores and so,
by 'copying' the affinity to the GPC we allow the cores to wake up
when needed. One of these usecases is the interrupt of the system
counter which acts as broadcast device.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>

Abel Vesa authored 5 years ago and Martin Kepplinger committed 5 years ago

i.MX8MQ is missing the wake_request signals from GIC to GPCv2. This indirectly
breaks cpuidle support due to inability to wake target cores on IPIs.

Here is the link to the errata (see e11171):

https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.nxp.com%2Fdocs%2Fen%2Ferrata%2FIMX8MDQLQ_0N14W.pdf&data=02%7C01%7Cabel.vesa%40nxp.com%7Cc93b9b273072461d4f2f08d6ed9d614a%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C1%7C636957657548550822&sdata=RjcDgljG%2FD5TPMP21bP5x%2F1l26KgdBgdBmEy1mwaLs4%3D&reserved=0



Now, in order to fix this, we can trigger IRQ 32 (hwirq 0) to all the cores by
setting 12th bit in IOMUX_GPR1 register. In order to control the target cores
only, that is, not waking up all the cores every time, we can unmask/mask the
IRQ 32 in the first GPC IMR register. So basically we can leave the IOMUX_GPR1
12th bit always set and just play with the masking and unmasking the IRO 32 for
each independent core.

Since EL3 is the one that deals with powering down/up the cores, and since the
cores wake up in EL3, EL3 should be the one to control the IMRs in this case.
This implies we need to get into EL3 on every IPI to do the unmasking, leaving
the masking to be done on the power-up sequence by the core itself.

In order to be able to get into EL3 on each IPI, we 'hijack' the registered smp
cross call handler, in this case the gic_raise_softirq which is registered by
the irq-gic-v3 driver and register our own handler instead. This new handler is
basically a wrapper over the hijacked handler plus the call into EL3.

To get into EL3, we use a custom vendor SIP id added just for this purpose.

All of this is conditional for i.MX8MQ only.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>

This reverts commit 62a96c05.

(as the commit below says:)
Some i.MX SoCs contain a system controller that is responsible for
controlling the state of the IPs that are present. Communication
between the host processor running an OS and the system controller
happens through a SCU protocol. This patch adds SCU protocol based
power domains drivers.

For more details, see commit c800cd78 ("firmware: imx: add SCU power domain
driver").

Signed-off-by: Martin Kepplinger <martin.kepplinger@puri.sm>

This reverts commit 6b19c01f.

Daniel Lezcano authored 5 years ago and Martin Kepplinger committed 5 years ago

Add a trip point above the one mitigated by cpufreq and the associated
idle cooling device. That allows to catch situation where the cpufreq
does not succeed to mitigate the temperature and where the idle
injection takes over to force CPU power down.

Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>

Daniel Lezcano authored 5 years ago and Martin Kepplinger committed 5 years ago

Register the PSCI generic cpuidle driver as a cooling device.

Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>

Daniel Lezcano authored 7 years ago and Martin Kepplinger committed 5 years ago

Register the ARM generic cpuidle driver as a cooling device.

Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>

Daniel Lezcano authored 7 years ago and Martin Kepplinger committed 5 years ago

The cpu idle cooling device offers a new method to cool down a CPU by
injecting idle cycles at runtime.

It has some similarities with the intel power clamp driver but it is
actually designed to work on the ARM architecture via the DT and using
the idle injection from the powercap framework.

The idle injection cycle is fixed while the running cycle is variable. That
allows to have control on the device reactivity for the user experience.

The DT definition makes the cooling device to point to an idle
state. Every idle states defined in the DT are potential cooling
devices. The cooling map does the binding between the cooling device
and the thermal zone. By this way, it is possible to choose which idle
state to inject.

An idle state powering down the CPU or the cluster will allow to drop
the static leakage, thus restoring the heat capacity of the SoC. It
can be set with a trip point between the hot and the critical points,
giving the opportunity to prevent a hard reset of the system when the
cpufreq cooling fails to cool down the CPU.

Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>

Daniel Lezcano authored 7 years ago and Martin Kepplinger committed 5 years ago

Provide some documentation for the idle injection cooling effect in
order to let people to understand the rational of the approach for the
idle injection CPU cooling device.

Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>

Daniel Lezcano authored 7 years ago and Martin Kepplinger committed 5 years ago

The next changes will add new way to cool down a CPU. In order to
sanitize and make the overall cpu cooling code consistent and robust
we must prevent the cpu cooling devices to co-exists with the same
purpose at the same time in the kernel.

Make the CPU cooling device a choice in the Kconfig, so only one CPU
cooling strategy can be chosen.

Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>

Daniel Lezcano authored 5 years ago and Martin Kepplinger committed 5 years ago

Currently the idle injection framework only allows to inject the
deepest idle state available on the system.

Give the opportunity to specify which idle state we want to inject by
adding a new function helper to set the state and use it when calling
play_idle().

There is no functional changes, the cpuidle state is the deepest one.

Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: Mathieu Poirier <mathieu.poirier@linaro.org>

Daniel Lezcano authored 5 years ago and Martin Kepplinger committed 5 years ago

Currently, the play_idle function does not allow to tell which idle
state we want to go. Improve this by passing the idle state as
parameter to the function.

Export cpuidle_find_deepest_state() symbol as it is used from the
intel_powerclamp driver as a module.

There is no functional changes, the cpuidle state is the deepest one.

Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: Mathieu Poirier <mathieu.poirier@linaro.org>

Daniel Lezcano authored 5 years ago and Martin Kepplinger committed 5 years ago

The play_idle function has two users, the intel powerclamp and the
idle_injection.

The idle injection cooling device uses the function via the
idle_injection powercap's APIs. Unfortunately, play_idle is currently
limited by the idle state depth: by default the deepest idle state is
selected. On the ARM[64] platforms, most of the time it is the cluster
idle state, the exit latency and the residency can be very high. That
reduces the scope of the idle injection usage because the impact on
the performances can be very significant.

If the idle injection cycles can be done with a shallow state like a
retention state, the cooling effect would eventually give similar
results than the cpufreq cooling device.

In order to prepare the function to receive an idle state parameter,
let's replace the 'use_deepest_state' boolean field with 'use_state'
and use this value to enter the specific idle state.

The current code keeps the default behavior which is go to the deepest
idle state.

Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: Mathieu Poirier <mathieu.poirier@linaro.org>

This reverts commit 7b55d5fc737a1196f22fee660ac9ed69a9917fe5.

This reverts commit 10721460fd1036f6b1f88aaa2a43fd1ae15e0ab5.

This reverts commit d21088bcf85b1e5dd0113d8ace277f82656c0a0c.

This reverts commit 127151845a5d5573c49d8debdee4339077a1d5dc.

This reverts commit 776db15086db7005da1cb6b7ca3e32de68e8e207.

This reverts commit 0ed0d17d9dcd3f729db898890e6507fcf968d723.

Signed-off-by: Martin Kepplinger <martin.kepplinger@puri.sm>

This reverts commit 0b4870bbe2889ff11e1483f09ee05f08895aa01e.

Upstream commit 4d28ba1d ("cpufreq: Add
imx-cpufreq-dt driver") is enough.

Lucas Stach authored 5 years ago and Guido Gunther committed 5 years ago

The switch to per-process address spaces erroneously dropped the check
which validated that the command buffer is mapped through the linear
apperture as required by the hardware. This turned a system
misconfiguration with a helpful error message into a very hard to
debug issue. Reinstate the check at the appropriate location.

Fixes: 17e4660a (drm/etnaviv: implement per-process address spaces on MMUv2)
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>

Signed-off-by: Guido Günther <guido.gunther@puri.sm>

This reverts commit 9f61faa653cb78df9ee4547c7c617e59097c242a.

Causes boot hang at

[    1.302069] loop: module loaded
[    1.306953] libphy: Fixed MDIO Bus: probed
[    1.313435] snvs_rtc 30370000.snvs:snvs-rtc-lp: registered as rtc0
[    1.319991] i2c /dev entries driver
[    1.328004] device-mapper: ioctl: 4.41.0-ioctl (2019-09-16) initialised: dm-devel@redhat.com
[    1.338525] sdhci: Secure Digital Host Controller Interface driver
[    1.344741] sdhci: Copyright(c) Pierre Ossman
[    1.349163] sdhci-pltfm: SDHCI platform and OF driver helper
...hang...

Needed for cpu idle

Signed-off-by: Guido Günther <guido.gunther@puri.sm>

Needed for the phone latest.

Signed-off-by: Guido Günther <guido.gunther@puri.sm>

Otherwise cpufreq fails to probe due to pmic driver probing bugs
fixed in linux-next.

Signed-off-by: Guido Günther <guido.gunther@puri.sm>

Otherwise it breaks mipi

Signed-off-by: Guido Günther <guido.gunther@puri.sm>

This reverts commit 87b1baf32040f405618902d31106296813c78811.

Fixes vt switching but makes the blank/unblank shift reappear.

Signed-off-by: Guido Günther <guido.gunther@puri.sm>

This allows to run without modules for the moment
and have a working display.

Signed-off-by: Guido Günther <guido.gunther@puri.sm>

Signed-off-by: Guido Günther <guido.gunther@puri.sm>

Angus Ainslie (Purism) authored 5 years ago and Guido Gunther committed 5 years ago

magnetometer

The LSM9DS1 uses a high level interrupt.

Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>

Angus Ainslie (Purism) authored 5 years ago and Guido Gunther committed 5 years ago

use vselect to set the io voltage to 1.8V

Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>

Angus Ainslie (Purism) authored 5 years ago and Guido Gunther committed 5 years ago

reinsterted
By adding broken-cd to the usdhc2 stanza the Redpine card can be
detected when the HKS is turned of and on.

Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>