• Peter Maydell's avatar
    target-arm: Widen thread-local register state fields to 64 bits · e4fe830b
    Peter Maydell authored
    The common pattern for system registers in a 64-bit capable ARM
    CPU is that when in AArch32 the cp15 register is a view of the
    bottom 32 bits of the 64-bit AArch64 system register; writes in
    AArch32 leave the top half unchanged. The most natural way to
    model this is to have the state field in the CPU struct be a
    64 bit value, and simply have the AArch32 TCG code operate on
    a pointer to its lower half.
    
    For aarch64-linux-user the only registers we need to share like
    this are the thread-local-storage ones. Widen their fields to
    64 bits and provide the 64 bit reginfo struct to make them
    visible in AArch64 state. Note that minor cleanup of the AArch64
    system register encoding space means We can share the TPIDR_EL1
    reginfo but need split encodings for TPIDR_EL0 and TPIDRRO_EL0.
    
    Since we're touching almost every line in QEMU that uses the
    c13_tls* fields in this patch anyway, we take the opportunity
    to rename them in line with the standard ARM architectural names
    for these registers.
    Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
    Reviewed-by: default avatarRichard Henderson <rth@twiddle.net>
    e4fe830b
target_cpu.h 1.06 KB