Commit 6f6260c7 authored by Blue Swirl's avatar Blue Swirl
Browse files

Sparc32: convert sparc32_dma to qdev


Signed-off-by: default avatarBlue Swirl <blauwirbel@gmail.com>
parent 430c7ec7
......@@ -21,9 +21,11 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "hw.h"
#include "sparc32_dma.h"
#include "sun4m.h"
#include "sysbus.h"
/* debug DMA */
//#define DEBUG_DMA
......@@ -60,6 +62,7 @@
typedef struct DMAState DMAState;
struct DMAState {
SysBusDevice busdev;
uint32_t dmaregs[DMA_REGS];
qemu_irq irq;
void *iommu;
......@@ -242,24 +245,56 @@ static int dma_load(QEMUFile *f, void *opaque, int version_id)
}
void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
void *iommu, qemu_irq **dev_irq, qemu_irq **reset)
void *iommu, qemu_irq *dev_irq, qemu_irq **reset)
{
DMAState *s;
int dma_io_memory;
DeviceState *dev;
SysBusDevice *s;
DMAState *d;
dev = qdev_create(NULL, "sparc32_dma");
qdev_set_prop_ptr(dev, "iommu_opaque", iommu);
qdev_init(dev);
s = sysbus_from_qdev(dev);
sysbus_connect_irq(s, 0, parent_irq);
*dev_irq = qdev_get_gpio_in(dev, 0);
sysbus_mmio_map(s, 0, daddr);
d = FROM_SYSBUS(DMAState, s);
*reset = &d->dev_reset;
return d;
}
s = qemu_mallocz(sizeof(DMAState));
static void sparc32_dma_init1(SysBusDevice *dev)
{
DMAState *s = FROM_SYSBUS(DMAState, dev);
int dma_io_memory;
s->irq = parent_irq;
s->iommu = iommu;
sysbus_init_irq(dev, &s->irq);
s->iommu = qdev_get_prop_ptr(&dev->qdev, "iommu_opaque");
dma_io_memory = cpu_register_io_memory(dma_mem_read, dma_mem_write, s);
cpu_register_physical_memory(daddr, DMA_SIZE, dma_io_memory);
sysbus_init_mmio(dev, DMA_SIZE, dma_io_memory);
register_savevm("sparc32_dma", daddr, 2, dma_save, dma_load, s);
register_savevm("sparc32_dma", -1, 2, dma_save, dma_load, s);
qemu_register_reset(dma_reset, s);
*dev_irq = qemu_allocate_irqs(dma_set_irq, s, 1);
*reset = &s->dev_reset;
qdev_init_gpio_in(&dev->qdev, dma_set_irq, 1);
}
return s;
static SysBusDeviceInfo sparc32_dma_info = {
.init = sparc32_dma_init1,
.qdev.name = "sparc32_dma",
.qdev.size = sizeof(DMAState),
.qdev.props = (DevicePropList[]) {
{.name = "iommu_opaque", .type = PROP_TYPE_PTR},
{.name = NULL}
}
};
static void sparc32_dma_register_devices(void)
{
sysbus_register_withprop(&sparc32_dma_info);
}
device_init(sparc32_dma_register_devices)
......@@ -3,7 +3,7 @@
/* sparc32_dma.c */
void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
void *iommu, qemu_irq **dev_irq, qemu_irq **reset);
void *iommu, qemu_irq *dev_irq, qemu_irq **reset);
void ledma_memory_read(void *opaque, target_phys_addr_t addr,
uint8_t *buf, int len, int do_bswap);
void ledma_memory_write(void *opaque, target_phys_addr_t addr,
......
......@@ -433,7 +433,7 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
unsigned int i;
void *iommu, *espdma, *ledma, *nvram;
qemu_irq *cpu_irqs[MAX_CPUS], *slavio_irq, *slavio_cpu_irq,
*espdma_irq, *ledma_irq;
espdma_irq, ledma_irq;
qemu_irq *esp_reset, *le_reset;
qemu_irq fdc_tc;
qemu_irq *cpu_halt;
......@@ -537,7 +537,7 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
tcx_init(hwdef->tcx_base, hwdef->vram_size, graphic_width, graphic_height,
graphic_depth);
lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq, le_reset);
nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
hwdef->nvram_size, 8);
......@@ -578,7 +578,7 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
esp_init(hwdef->esp_base, 2,
espdma_memory_read, espdma_memory_write,
espdma, *espdma_irq, esp_reset);
espdma, espdma_irq, esp_reset);
if (hwdef->cs_base)
cs_init(hwdef->cs_base, hwdef->cs_irq, slavio_intctl);
......@@ -1223,7 +1223,7 @@ static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
unsigned int i;
void *iounits[MAX_IOUNITS], *espdma, *ledma, *nvram, *sbi;
qemu_irq *cpu_irqs[MAX_CPUS], *sbi_irq, *sbi_cpu_irq,
*espdma_irq, *ledma_irq;
espdma_irq, ledma_irq;
qemu_irq *esp_reset, *le_reset;
ram_addr_t ram_offset, prom_offset;
unsigned long kernel_size;
......@@ -1315,7 +1315,7 @@ static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
tcx_init(hwdef->tcx_base, hwdef->vram_size, graphic_width, graphic_height,
graphic_depth);
lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq, le_reset);
nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0,
hwdef->nvram_size, 8);
......@@ -1337,7 +1337,7 @@ static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
esp_init(hwdef->esp_base, 2,
espdma_memory_read, espdma_memory_write,
espdma, *espdma_irq, esp_reset);
espdma, espdma_irq, esp_reset);
kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
RAM_size);
......@@ -1443,7 +1443,7 @@ static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
{
CPUState *env;
void *iommu, *espdma, *ledma, *nvram;
qemu_irq *cpu_irqs, *slavio_irq, *espdma_irq, *ledma_irq;
qemu_irq *cpu_irqs, *slavio_irq, espdma_irq, ledma_irq;
qemu_irq *esp_reset, *le_reset;
qemu_irq fdc_tc;
ram_addr_t ram_offset, prom_offset;
......@@ -1528,7 +1528,7 @@ static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
tcx_init(hwdef->tcx_base, hwdef->vram_size, graphic_width, graphic_height,
graphic_depth);
lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq, le_reset);
nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
hwdef->nvram_size, 2);
......@@ -1562,7 +1562,7 @@ static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
esp_init(hwdef->esp_base, 2,
espdma_memory_read, espdma_memory_write,
espdma, *espdma_irq, esp_reset);
espdma, espdma_irq, esp_reset);
kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
RAM_size);
......
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