Commit a08d4367 authored by Jan Kiszka's avatar Jan Kiszka Committed by Anthony Liguori
Browse files

Revert "Introduce reset notifier order"

This reverts commit 8217606e

 (and
updates later added users of qemu_register_reset), we solved the
problem it originally addressed less invasively.
Signed-off-by: default avatarJan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: default avatarAnthony Liguori <aliguori@us.ibm.com>
parent a62acdc0
......@@ -1369,7 +1369,7 @@ int ac97_init (PCIBus *bus)
pci_register_bar (&d->dev, 0, 256 * 4, PCI_ADDRESS_SPACE_IO, ac97_map);
pci_register_bar (&d->dev, 1, 64 * 4, PCI_ADDRESS_SPACE_IO, ac97_map);
register_savevm ("ac97", 0, 2, ac97_save, ac97_load, s);
qemu_register_reset (ac97_on_reset, 0, s);
qemu_register_reset (ac97_on_reset, s);
AUD_register_card ("ac97", &s->card);
ac97_on_reset (s);
return 0;
......
......@@ -550,7 +550,7 @@ i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
s->smbus = i2c_init_bus(NULL, "i2c");
s->irq = sci_irq;
qemu_register_reset(piix4_reset, 0, s);
qemu_register_reset(piix4_reset, s);
return s->smbus;
}
......
......@@ -122,7 +122,7 @@ ADBDevice *adb_register_device(ADBBusState *s, int devaddr,
d->devreq = devreq;
d->devreset = devreset;
d->opaque = opaque;
qemu_register_reset((QEMUResetHandler *)devreset, 0, d);
qemu_register_reset((QEMUResetHandler *)devreset, d);
d->devreset(d);
return d;
}
......
......@@ -998,7 +998,7 @@ int apic_init(CPUState *env)
s->timer = qemu_new_timer(vm_clock, apic_timer, s);
register_savevm("apic", s->idx, 2, apic_save, apic_load, s);
qemu_register_reset(apic_reset, 0, s);
qemu_register_reset(apic_reset, s);
local_apics[s->idx] = s;
return 0;
......
......@@ -203,7 +203,7 @@ void arm_load_kernel(CPUState *env, struct arm_boot_info *info)
if (info->nb_cpus == 0)
info->nb_cpus = 1;
env->boot_info = info;
qemu_register_reset(main_cpu_reset, 0, env);
qemu_register_reset(main_cpu_reset, env);
}
/* Assume that raw images are linux kernels, and ELF images are not. */
......
......@@ -271,7 +271,7 @@ void axisdev88_init (ram_addr_t ram_size,
cpu_model = "crisv32";
}
env = cpu_init(cpu_model);
qemu_register_reset(main_cpu_reset, 0, env);
qemu_register_reset(main_cpu_reset, env);
/* allocate RAM */
phys_ram = qemu_ram_alloc(ram_size);
......
......@@ -3228,7 +3228,7 @@ static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci)
s->vga.cursor_invalidate = cirrus_cursor_invalidate;
s->vga.cursor_draw_line = cirrus_cursor_draw_line;
qemu_register_reset(cirrus_reset, 0, s);
qemu_register_reset(cirrus_reset, s);
cirrus_reset(s);
register_savevm("cirrus_vga", 0, 2, cirrus_vga_save, cirrus_vga_load, s);
}
......
......@@ -175,6 +175,6 @@ void cs_init(target_phys_addr_t base, int irq, void *intctl)
cs_io_memory = cpu_register_io_memory(cs_mem_read, cs_mem_write, s);
cpu_register_physical_memory(base, CS_SIZE, cs_io_memory);
register_savevm("cs4231", base, 1, cs_save, cs_load, s);
qemu_register_reset(cs_reset, 0, s);
qemu_register_reset(cs_reset, s);
cs_reset(s);
}
......@@ -656,7 +656,7 @@ int cs4231a_init (qemu_irq *pic)
DMA_register_channel (s->dma, cs_dma_read, s);
register_savevm ("cs4231a", 0, 1, cs_save, cs_load, s);
qemu_register_reset (cs_reset, 0, s);
qemu_register_reset (cs_reset, s);
cs_reset (s);
AUD_register_card ("cs4231a", &s->card);
......
......@@ -762,6 +762,6 @@ void cuda_init (int *cuda_mem_index, qemu_irq irq)
s->adb_poll_timer = qemu_new_timer(vm_clock, cuda_adb_poll, s);
*cuda_mem_index = cpu_register_io_memory(cuda_read, cuda_write, s);
register_savevm("cuda", -1, 1, cuda_save, cuda_load, s);
qemu_register_reset(cuda_reset, 0, s);
qemu_register_reset(cuda_reset, s);
cuda_reset(s);
}
......@@ -493,7 +493,7 @@ static void dma_init2(struct dma_cont *d, int base, int dshift,
register_ioport_read (base + ((i + 8) << dshift), 1, 1,
read_cont, d);
}
qemu_register_reset(dma_reset, 0, d);
qemu_register_reset(dma_reset, d);
dma_reset(d);
for (i = 0; i < ARRAY_SIZE (d->regs); ++i) {
d->regs[i].transfer_handler = dma_phony_handler;
......
......@@ -894,7 +894,7 @@ void dp83932_init(NICInfo *nd, target_phys_addr_t base, int it_shift,
nic_receive, NULL, nic_cleanup, s);
qemu_format_nic_info_str(s->vc, nd->macaddr);
qemu_register_reset(nic_reset, 0, s);
qemu_register_reset(nic_reset, s);
nic_reset(s);
s->mmio_index = cpu_register_io_memory(dp8393x_read, dp8393x_write, s);
......
......@@ -1121,7 +1121,7 @@ static void pci_e1000_init(PCIDevice *pci_dev)
register_savevm(info_str, -1, 2, nic_save, nic_load, d);
d->dev.unregister = pci_e1000_uninit;
qemu_register_reset(e1000_reset, 0, d);
qemu_register_reset(e1000_reset, d);
e1000_reset(d);
}
......
......@@ -334,7 +334,7 @@ void * ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version)
ecc_io_memory);
}
register_savevm("ECC", base, 3, ecc_save, ecc_load, s);
qemu_register_reset(ecc_reset, 0, s);
qemu_register_reset(ecc_reset, s);
ecc_reset(s);
return s;
}
......@@ -1772,7 +1772,7 @@ static void nic_init(PCIDevice *pci_dev, uint32_t device)
qemu_format_nic_info_str(s->vc, s->macaddr);
qemu_register_reset(nic_reset, 0, s);
qemu_register_reset(nic_reset, s);
register_savevm(s->vc->model, -1, 3, nic_save, nic_load, s);
}
......
......@@ -1055,7 +1055,7 @@ int es1370_init (PCIBus *bus)
pci_register_bar (&d->dev, 0, 256, PCI_ADDRESS_SPACE_IO, es1370_map);
register_savevm ("es1370", 0, 2, es1370_save, es1370_load, s);
qemu_register_reset (es1370_on_reset, 0, s);
qemu_register_reset (es1370_on_reset, s);
AUD_register_card ("es1370", &s->card);
es1370_reset (s);
......
......@@ -758,7 +758,7 @@ int escc_init(target_phys_addr_t base, qemu_irq irqA, qemu_irq irqB,
register_savevm("escc", base, 2, escc_save, escc_load, s);
else
register_savevm("escc", -1, 2, escc_save, escc_load, s);
qemu_register_reset(escc_reset, 0, s);
qemu_register_reset(escc_reset, s);
escc_reset(s);
return escc_io_memory;
}
......@@ -932,6 +932,6 @@ void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq,
"QEMU Sun Mouse");
qemu_add_kbd_event_handler(sunkbd_event, &s->chn[1]);
register_savevm("slavio_serial_mouse", base, 2, escc_save, escc_load, s);
qemu_register_reset(escc_reset, 0, s);
qemu_register_reset(escc_reset, s);
escc_reset(s);
}
......@@ -680,7 +680,7 @@ static void esp_init1(SysBusDevice *dev)
esp_reset(s);
register_savevm("esp", -1, 3, esp_save, esp_load, s);
qemu_register_reset(esp_reset, 0, s);
qemu_register_reset(esp_reset, s);
qdev_init_gpio_in(&dev->qdev, parent_esp_reset, 1);
......
......@@ -65,7 +65,7 @@ void bareetraxfs_init (ram_addr_t ram_size,
cpu_model = "crisv32";
}
env = cpu_init(cpu_model);
qemu_register_reset(main_cpu_reset, 0, env);
qemu_register_reset(main_cpu_reset, env);
/* allocate RAM */
phys_ram = qemu_ram_alloc(ram_size);
......
......@@ -326,7 +326,7 @@ static void etraxfs_timer_init(SysBusDevice *dev)
timer_regs = cpu_register_io_memory(timer_read, timer_write, t);
sysbus_init_mmio(dev, 0x5c, timer_regs);
qemu_register_reset(etraxfs_timer_reset, 0, t);
qemu_register_reset(etraxfs_timer_reset, t);
}
static void etraxfs_timer_register(void)
......
......@@ -1883,7 +1883,7 @@ static fdctrl_t *fdctrl_init_common (qemu_irq irq, int dma_chann,
}
fdctrl_external_reset(fdctrl);
register_savevm("fdc", io_base, 2, fdc_save, fdc_load, fdctrl);
qemu_register_reset(fdctrl_external_reset, 0, fdctrl);
qemu_register_reset(fdctrl_external_reset, fdctrl);
for (i = 0; i < MAX_FD; i++) {
fd_revalidate(&fdctrl->drives[i]);
}
......
......@@ -281,7 +281,7 @@ void *fw_cfg_init(uint32_t ctl_port, uint32_t data_port,
fw_cfg_add_i16(s, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
register_savevm("fw_cfg", -1, 1, fw_cfg_save, fw_cfg_load, s);
qemu_register_reset(fw_cfg_reset, 0, s);
qemu_register_reset(fw_cfg_reset, s);
fw_cfg_reset(s);
return s;
......
......@@ -598,7 +598,7 @@ int g364fb_mm_init(target_phys_addr_t vram_base,
s->vram = qemu_get_ram_ptr(s->vram_offset);
s->irq = irq;
qemu_register_reset(g364fb_reset, 0, s);
qemu_register_reset(g364fb_reset, s);
register_savevm("g364fb", 0, 1, g364fb_save, g364fb_load, s);
g364fb_reset(s);
......
......@@ -177,7 +177,7 @@ PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic)
d->config[0x27] = 0x85;
#endif
register_savevm("grackle", 0, 1, pci_grackle_save, pci_grackle_load, d);
qemu_register_reset(pci_grackle_reset, 0, d);
qemu_register_reset(pci_grackle_reset, d);
pci_grackle_reset(d);
return s->bus;
......
......@@ -230,7 +230,7 @@ qemu_irq *heathrow_pic_init(int *pmem_index,
register_savevm("heathrow_pic", -1, 1, heathrow_pic_save,
heathrow_pic_load, s);
qemu_register_reset(heathrow_pic_reset, 0, s);
qemu_register_reset(heathrow_pic_reset, s);
heathrow_pic_reset(s);
return qemu_allocate_irqs(heathrow_pic_set_irq, s, 64);
}
......@@ -580,7 +580,7 @@ void hpet_init(qemu_irq *irq) {
}
hpet_reset(s);
register_savevm("hpet", -1, 1, hpet_save, hpet_load, s);
qemu_register_reset(hpet_reset, 0, s);
qemu_register_reset(hpet_reset, s);
/* HPET Area */
iomemtype = cpu_register_io_memory(hpet_ram_read,
hpet_ram_write, s);
......
......@@ -259,7 +259,7 @@ void unregister_savevm(const char *idstr, void *opaque);
typedef void QEMUResetHandler(void *opaque);
void qemu_register_reset(QEMUResetHandler *func, int order, void *opaque);
void qemu_register_reset(QEMUResetHandler *func, void *opaque);
/* handler to set the boot_device for a specific type of QEMUMachine */
/* return 0 if success */
......
......@@ -497,7 +497,7 @@ PITState *pit_init(int base, qemu_irq irq)
register_savevm("i8254", base, 1, pit_save, pit_load, pit);
qemu_register_reset(pit_reset, 0, pit);
qemu_register_reset(pit_reset, pit);
register_ioport_write(base, 4, 1, pit_ioport_write, pit);
register_ioport_read(base, 3, 1, pit_ioport_read, pit);
......
......@@ -508,7 +508,7 @@ static void pic_init1(int io_addr, int elcr_addr, PicState *s)
register_ioport_read(elcr_addr, 1, 1, elcr_ioport_read, s);
}
register_savevm("i8259", io_addr, 1, pic_save, pic_load, s);
qemu_register_reset(pic_reset, 0, s);
qemu_register_reset(pic_reset, s);
}
void pic_info(Monitor *mon)
......
......@@ -3340,7 +3340,7 @@ void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
ide_init2(&d->ide_if[2], hd_table[2], hd_table[3], irq[1]);
register_savevm("ide", 0, 2, pci_ide_save, pci_ide_load, d);
qemu_register_reset(cmd646_reset, 0, d);
qemu_register_reset(cmd646_reset, d);
cmd646_reset(d);
}
......@@ -3383,7 +3383,7 @@ void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE);
pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
qemu_register_reset(piix3_reset, 0, d);
qemu_register_reset(piix3_reset, d);
piix3_reset(d);
pci_register_bar((PCIDevice *)d, 4, 0x10,
......@@ -3423,7 +3423,7 @@ void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE);
pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
qemu_register_reset(piix3_reset, 0, d);
qemu_register_reset(piix3_reset, d);
piix3_reset(d);
pci_register_bar((PCIDevice *)d, 4, 0x10,
......@@ -3764,7 +3764,7 @@ int pmac_ide_init (BlockDriverState **hd_table, qemu_irq irq,
pmac_ide_memory = cpu_register_io_memory(pmac_ide_read,
pmac_ide_write, d);
register_savevm("ide", 0, 1, pmac_ide_save, pmac_ide_load, d);
qemu_register_reset(pmac_ide_reset, 0, d);
qemu_register_reset(pmac_ide_reset, d);
pmac_ide_reset(d);
return pmac_ide_memory;
......
......@@ -255,7 +255,7 @@ IOAPICState *ioapic_init(void)
cpu_register_physical_memory(0xfec00000, 0x1000, io_memory);
register_savevm("ioapic", 0, 1, ioapic_save, ioapic_load, s);
qemu_register_reset(ioapic_reset, 0, s);
qemu_register_reset(ioapic_reset, s);
return s;
}
......@@ -379,7 +379,7 @@ void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq)
cpu_register_physical_memory(addr, IOMMU_NREGS * 4, iommu_io_memory);
register_savevm("iommu", addr, 2, iommu_save, iommu_load, s);
qemu_register_reset(iommu_reset, 0, s);
qemu_register_reset(iommu_reset, s);
iommu_reset(s);
return s;
}
......@@ -501,7 +501,7 @@ static void lm8323_init(i2c_slave *i2c)
lm_kbd_reset(s);
qemu_register_reset((void *) lm_kbd_reset, 0, s);
qemu_register_reset((void *) lm_kbd_reset, s);
register_savevm("LM8323", -1, 0, lm_kbd_save, lm_kbd_load, s);
}
......
......@@ -641,7 +641,7 @@ m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr_t mem_base,
}
qemu_get_timedate(&s->alarm, 0);
qemu_register_reset(m48t59_reset, 0, s);
qemu_register_reset(m48t59_reset, s);
save_base = mem_base ? mem_base : io_base;
register_savevm("m48t59", save_base, 1, m48t59_save, m48t59_load, s);
......
......@@ -839,7 +839,7 @@ void* DBDMA_init (int *dbdma_mem_index)
*dbdma_mem_index = cpu_register_io_memory(dbdma_read, dbdma_write, s);
register_savevm("dbdma", -1, 1, dbdma_save, dbdma_load, s);
qemu_register_reset(dbdma_reset, 0, s);
qemu_register_reset(dbdma_reset, s);
dbdma_reset(s);
dbdma_bh = qemu_bh_new(DBDMA_run_bh, s);
......
......@@ -142,7 +142,7 @@ MacIONVRAMState *macio_nvram_init (int *mem_index, target_phys_addr_t size,
*mem_index = s->mem_index;
register_savevm("macio_nvram", -1, 1, macio_nvram_save, macio_nvram_load,
s);
qemu_register_reset(macio_nvram_reset, 0, s);
qemu_register_reset(macio_nvram_reset, s);
macio_nvram_reset(s);
return s;
......
......@@ -626,7 +626,7 @@ RTCState *rtc_init_sqw(int base, qemu_irq irq, qemu_irq sqw_irq, int base_year)
if (rtc_td_hack)
register_savevm("mc146818rtc-td", base, 1, rtc_save_td, rtc_load_td, s);
#endif
qemu_register_reset(rtc_reset, 0, s);
qemu_register_reset(rtc_reset, s);
return s;
}
......@@ -743,6 +743,6 @@ RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq,
if (rtc_td_hack)
register_savevm("mc146818rtc-td", base, 1, rtc_save_td, rtc_load_td, s);
#endif
qemu_register_reset(rtc_reset, 0, s);
qemu_register_reset(rtc_reset, s);
return s;
}
......@@ -146,7 +146,7 @@ void mips_jazz_init (ram_addr_t ram_size,
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
qemu_register_reset(main_cpu_reset, 0, env);
qemu_register_reset(main_cpu_reset, env);
/* allocate RAM */
ram_offset = qemu_ram_alloc(ram_size);
......
......@@ -447,7 +447,7 @@ static MaltaFPGAState *malta_fpga_init(target_phys_addr_t base, qemu_irq uart_ir
s->uart = serial_mm_init(base + 0x900, 3, uart_irq, 230400, uart_chr, 1);
malta_fpga_reset(s);
qemu_register_reset(malta_fpga_reset, 0, s);
qemu_register_reset(malta_fpga_reset, s);
return s;
}
......@@ -792,7 +792,7 @@ void mips_malta_init (ram_addr_t ram_size,
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
qemu_register_reset(main_cpu_reset, 0, env);
qemu_register_reset(main_cpu_reset, env);
/* allocate RAM */
if (ram_size > (256 << 20)) {
......
......@@ -126,7 +126,7 @@ mips_mipssim_init (ram_addr_t ram_size,
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
qemu_register_reset(main_cpu_reset, 0, env);
qemu_register_reset(main_cpu_reset, env);
/* Allocate RAM. */
ram_offset = qemu_ram_alloc(ram_size);
......
......@@ -171,7 +171,7 @@ void mips_r4k_init (ram_addr_t ram_size,
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
qemu_register_reset(main_cpu_reset, 0, env);
qemu_register_reset(main_cpu_reset, env);
/* allocate RAM */
if (ram_size > (256 << 20)) {
......
......@@ -441,7 +441,7 @@ static i2c_interface *musicpal_audio_init(qemu_irq irq)
musicpal_audio_writefn, s);
cpu_register_physical_memory(MP_AUDIO_BASE, MP_AUDIO_SIZE, iomemtype);
qemu_register_reset(musicpal_audio_reset, 0, s);
qemu_register_reset(musicpal_audio_reset, s);
return i2c;
}
......@@ -1047,7 +1047,7 @@ static void mv88w8618_pic_init(SysBusDevice *dev)
mv88w8618_pic_writefn, s);
sysbus_init_mmio(dev, MP_PIC_SIZE, iomemtype);
qemu_register_reset(mv88w8618_pic_reset, 0, s);
qemu_register_reset(mv88w8618_pic_reset, s);
}
/* PIT register offsets */
......
......@@ -1329,7 +1329,7 @@ static void n8x0_init(ram_addr_t ram_size, const char *boot_device,
binfo->initrd_filename = initrd_filename;
arm_load_kernel(s->cpu->env, binfo);
qemu_register_reset(n8x0_boot_init, 0, s);
qemu_register_reset(n8x0_boot_init, s);
n8x0_boot_init(s);
}
......
......@@ -4797,7 +4797,7 @@ struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size,
omap_setup_dsp_mapping(omap15xx_dsp_mm);
omap_setup_mpui_io(s);
qemu_register_reset(omap1_mpu_reset, 0, s);
qemu_register_reset(omap1_mpu_reset, s);
return s;
}
......@@ -4868,7 +4868,7 @@ struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
* GPMC registers 6800a000 6800afff
*/
qemu_register_reset(omap2_mpu_reset, 0, s);
qemu_register_reset(omap2_mpu_reset, s);
return s;
}
......@@ -1249,7 +1249,7 @@ qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus,
opp->need_swap = 1;
register_savevm("openpic", 0, 2, openpic_save, openpic_load, opp);
qemu_register_reset(openpic_reset, 0, opp);
qemu_register_reset(openpic_reset, opp);
opp->irq_raise = openpic_irq_raise;
opp->reset = openpic_reset;
......@@ -1709,7 +1709,7 @@ qemu_irq *mpic_init (target_phys_addr_t base, int nb_cpus,
mpp->reset = mpic_reset;
register_savevm("mpic", 0, 2, openpic_save, openpic_load, mpp);
qemu_register_reset(mpic_reset, 0, mpp);
qemu_register_reset(mpic_reset, mpp);
mpp->reset(mpp);
return qemu_allocate_irqs(openpic_set_irq, mpp, mpp->max_irq);
......
......@@ -448,7 +448,7 @@ ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr)
s->irq = irq;
s->chr = chr;
parallel_reset(s);
qemu_register_reset(parallel_reset, 0, s);
qemu_register_reset(parallel_reset, s);
if (qemu_chr_ioctl(chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) {
s->hw_driver = 1;
......@@ -541,7 +541,7 @@ ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq
s->chr = chr;
s->it_shift = it_shift;
parallel_reset(s);
qemu_register_reset(parallel_reset, 0, s);
qemu_register_reset(parallel_reset, s);
io_sw = cpu_register_io_memory(parallel_mm_read_sw, parallel_mm_write_sw, s);
cpu_register_physical_memory(base, 8 << it_shift, io_sw);
......
......@@ -84,7 +84,7 @@ static void option_rom_setup_reset(target_phys_addr_t addr, unsigned size)
cpu_physical_memory_read(addr, rrd->data, size);
rrd->addr = addr;
rrd->size = size;
qemu_register_reset(option_rom_reset, 0, rrd);
qemu_register_reset(option_rom_reset, rrd);
}
static void ioport80_write(void *opaque, uint32_t addr, uint32_t data)
......@@ -1115,7 +1115,7 @@ static void pc_init1(ram_addr_t ram_size,
/* APIC reset callback resets cpu */
apic_init(env);
} else {
qemu_register_reset((QEMUResetHandler*)cpu_reset, 0, env);
qemu_register_reset((QEMUResetHandler*)cpu_reset, env);
}
}
......
......@@ -120,7 +120,7 @@ PCIBus *pci_register_bus(DeviceState *parent, const char *name,
bus->next = first_bus;
first_bus = bus;
register_savevm("PCIBUS", nbus++, 1, pcibus_save, pcibus_load, bus);
qemu_register_reset(pci_bus_reset, 0, bus);
qemu_register_reset(pci_bus_reset, bus);
return bus;
}
......
......@@ -381,7 +381,7 @@ void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base)
#ifdef TARGET_I386
vmmouse_init(s->mouse);
#endif
qemu_register_reset(kbd_reset, 0, s);
qemu_register_reset(kbd_reset, s);
}
/* Memory mapped interface */
......@@ -438,5 +438,5 @@ void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
#ifdef TARGET_I386
vmmouse_init(s->mouse);
#endif
qemu_register_reset(kbd_reset, 0, s);
qemu_register_reset(kbd_reset, s);
}
......@@ -120,7 +120,7 @@ petalogix_s3adsp1800_init(ram_addr_t ram_size,
env = cpu_init(cpu_model);
env->pvr.regs[10] = 0x0c000000; /* spartan 3a dsp family. */
qemu_register_reset(main_cpu_reset, 0, env);
qemu_register_reset(main_cpu_reset, env);
/* Attach emulated BRAM through the LMB. */
phys_lmb_bram = qemu_ram_alloc(LMB_BRAM_SIZE);
......