Commit afbb5194 authored by balrog's avatar balrog

Handle on-chip DMA controllers in one place, convert OMAP DMA to use it.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4920 c046a42c-6fe2-441c-8c8c-71466251a162
parent 51fec3cc
......@@ -594,7 +594,7 @@ OBJS+= pxa2xx_lcd.o pxa2xx_mmci.o pxa2xx_pcmcia.o pxa2xx_keypad.o
OBJS+= pflash_cfi01.o gumstix.o
OBJS+= zaurus.o ide.o serial.o nand.o ecc.o spitz.o tosa.o tc6393xb.o
OBJS+= omap1.o omap_lcdc.o omap_dma.o omap_clk.o omap_mmc.o omap_i2c.o
OBJS+= omap2.o omap_dss.o
OBJS+= omap2.o omap_dss.o soc_dma.o
OBJS+= palm.o tsc210x.o
OBJS+= nseries.o blizzard.o onenand.o vga.o cbus.o tusb6010.o usb-musb.o
OBJS+= tsc2005.o
......
......@@ -417,14 +417,14 @@ enum omap_dma_model {
omap_dma_4,
};
struct omap_dma_s;
struct omap_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs,
struct soc_dma_s;
struct soc_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs,
qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk,
enum omap_dma_model model);
struct omap_dma_s *omap_dma4_init(target_phys_addr_t base, qemu_irq *irqs,
struct soc_dma_s *omap_dma4_init(target_phys_addr_t base, qemu_irq *irqs,
struct omap_mpu_state_s *mpu, int fifo,
int chans, omap_clk iclk, omap_clk fclk);
void omap_dma_reset(struct omap_dma_s *s);
void omap_dma_reset(struct soc_dma_s *s);
struct dma_irq_map {
int ih;
......@@ -494,7 +494,7 @@ struct omap_dma_lcd_channel_s {
ram_addr_t phys_framebuffer[2];
qemu_irq irq;
struct omap_mpu_state_s *mpu;
} *omap_dma_get_lcdch(struct omap_dma_s *s);
} *omap_dma_get_lcdch(struct soc_dma_s *s);
/*
* DMA request numbers for OMAP1
......@@ -882,7 +882,7 @@ struct omap_mpu_state_s {
/* MPU private TIPB peripherals */
struct omap_intr_handler_s *ih[2];
struct omap_dma_s *dma;
struct soc_dma_s *dma;
struct omap_mpu_timer_s *timer[3];
struct omap_watchdog_timer_s *wdt;
......
......@@ -24,6 +24,7 @@
#include "sysemu.h"
#include "qemu-timer.h"
#include "qemu-char.h"
#include "soc_dma.h"
/* We use pc-style serial ports. */
#include "pc.h"
......@@ -4704,6 +4705,12 @@ struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size,
s->port[local ].addr_valid = omap_validate_local_addr;
s->port[tipb_mpui].addr_valid = omap_validate_tipb_mpui_addr;
/* Register SDRAM and SRAM DMA ports for fast transfers. */
soc_dma_port_add_mem_ram(s->dma,
emiff_base, OMAP_EMIFF_BASE, s->sdram_size);
soc_dma_port_add_mem_ram(s->dma,
imif_base, OMAP_IMIF_BASE, s->sram_size);
s->timer[0] = omap_mpu_timer_init(0xfffec500,
s->irq[0][OMAP_INT_TIMER1],
omap_findclk(s, "mputim_ck"));
......
......@@ -26,6 +26,7 @@
#include "qemu-timer.h"
#include "qemu-char.h"
#include "flash.h"
#include "soc_dma.h"
#include "audio/audio.h"
/* GP timers */
......@@ -4493,6 +4494,10 @@ struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
omap_findclk(s, "sdma_fclk"));
s->port->addr_valid = omap2_validate_addr;
/* Register SDRAM and SRAM ports for fast DMA transfers. */
soc_dma_port_add_mem_ram(s->dma, q2_base, OMAP2_Q2_BASE, s->sdram_size);
soc_dma_port_add_mem_ram(s->dma, sram_base, OMAP2_SRAM_BASE, s->sram_size);
s->uart[0] = omap2_uart_init(omap_l4ta(s->l4, 19),
s->irq[0][OMAP_INT_24XX_UART1_IRQ],
omap_findclk(s, "uart1_fclk"),
......
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/*
* On-chip DMA controller framework.
*
* Copyright (C) 2008 Nokia Corporation
* Written by Andrzej Zaborowski <andrew@openedhand.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 or
* (at your option) version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
struct soc_dma_s;
struct soc_dma_ch_s;
typedef void (*soc_dma_io_t)(void *opaque, uint8_t *buf, int len);
typedef void (*soc_dma_transfer_t)(struct soc_dma_ch_s *ch);
enum soc_dma_port_type {
soc_dma_port_mem,
soc_dma_port_fifo,
soc_dma_port_other,
};
enum soc_dma_access_type {
soc_dma_access_const,
soc_dma_access_linear,
soc_dma_access_other,
};
struct soc_dma_ch_s {
/* Private */
struct soc_dma_s *dma;
int num;
QEMUTimer *timer;
/* Set by soc_dma.c */
int enable;
int update;
/* This should be set by dma->setup_fn(). */
int bytes;
/* Initialised by the DMA module, call soc_dma_ch_update after writing. */
enum soc_dma_access_type type[2];
target_phys_addr_t vaddr[2]; /* Updated by .transfer_fn(). */
/* Private */
void *paddr[2];
soc_dma_io_t io_fn[2];
void *io_opaque[2];
int running;
soc_dma_transfer_t transfer_fn;
/* Set and used by the DMA module. */
void *opaque;
};
struct soc_dma_s {
/* Following fields are set by the SoC DMA module and can be used
* by anybody. */
uint64_t drqbmp; /* Is zeroed by soc_dma_reset() */
qemu_irq *drq;
void *opaque;
int64_t freq;
soc_dma_transfer_t transfer_fn;
soc_dma_transfer_t setup_fn;
/* Set by soc_dma_init() for use by the DMA module. */
struct soc_dma_ch_s *ch;
};
/* Call to activate or stop a DMA channel. */
void soc_dma_set_request(struct soc_dma_ch_s *ch, int level);
/* Call after every write to one of the following fields and before
* calling soc_dma_set_request(ch, 1):
* ch->type[0...1],
* ch->vaddr[0...1],
* ch->paddr[0...1],
* or after a soc_dma_port_add_fifo() or soc_dma_port_add_mem(). */
void soc_dma_ch_update(struct soc_dma_ch_s *ch);
/* The SoC should call this when the DMA module is being reset. */
void soc_dma_reset(struct soc_dma_s *s);
struct soc_dma_s *soc_dma_init(int n);
void soc_dma_port_add_fifo(struct soc_dma_s *dma, target_phys_addr_t virt_base,
soc_dma_io_t fn, void *opaque, int out);
void soc_dma_port_add_mem(struct soc_dma_s *dma, uint8_t *phys_base,
target_phys_addr_t virt_base, size_t size);
static inline void soc_dma_port_add_fifo_in(struct soc_dma_s *dma,
target_phys_addr_t virt_base, soc_dma_io_t fn, void *opaque)
{
return soc_dma_port_add_fifo(dma, virt_base, fn, opaque, 0);
}
static inline void soc_dma_port_add_fifo_out(struct soc_dma_s *dma,
target_phys_addr_t virt_base, soc_dma_io_t fn, void *opaque)
{
return soc_dma_port_add_fifo(dma, virt_base, fn, opaque, 1);
}
static inline void soc_dma_port_add_mem_ram(struct soc_dma_s *dma,
ram_addr_t offset, target_phys_addr_t virt_base, size_t size)
{
return soc_dma_port_add_mem(dma, phys_ram_base + offset, virt_base, size);
}
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