Commit ee6847d1 authored by Gerd Hoffmann's avatar Gerd Hoffmann Committed by Anthony Liguori

qdev: rework device properties.

This patch is a major overhaul of the device properties.  The properties
are saved directly in the device state struct now, the linked list of
property values is gone.

Advantages:
  * We don't have to maintain the list with the property values.
  * The value in the property list and the value actually used by
    the device can't go out of sync any more (used to happen for
    the pci.devfn == -1 case) because there is only one place where
    the value is stored.
  * A record describing the property is required now, you can't set
    random properties any more.

There are bus-specific and device-specific properties.  The former
should be used for properties common to all bus drivers.  Typical
use case is bus addressing, i.e. pci.devfn and i2c.address.

Properties have a PropertyInfo struct attached with name, size and
function pointers to parse and print properties.  A few common property
types have PropertyInfos defined in qdev-properties.c.  Drivers are free
to implement their own very special property parsers if needed.

Properties can have default values.  If unset they are zero-filled.
Signed-off-by: default avatarGerd Hoffmann <kraxel@redhat.com>
Signed-off-by: default avatarAnthony Liguori <aliguori@us.ibm.com>
parent f114784f
......@@ -108,7 +108,7 @@ obj-y += bt-hci-csr.o
obj-y += buffered_file.o migration.o migration-tcp.o net.o qemu-sockets.o
obj-y += qemu-char.o aio.o net-checksum.o savevm.o cache-utils.o
obj-y += msmouse.o ps2.o
obj-y += qdev.o ssi.o
obj-y += qdev.o qdev-properties.o ssi.o
obj-$(CONFIG_BRLAPI) += baum.o
......
......@@ -26,7 +26,7 @@ obj-y += m48t59.o escc.o
# SCSI layer
obj-y += lsi53c895a.o esp.o
obj-y += dma-helpers.o sysbus.o
obj-y += dma-helpers.o sysbus.o qdev-addr.o
all: $(HWLIB)
# Dummy command so that make thinks it has done something
......
......@@ -194,7 +194,6 @@ static void arm_sysctl_init1(SysBusDevice *dev)
arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, dev);
int iomemtype;
s->sys_id = qdev_get_prop_int(&dev->qdev, "sys_id", 0);
/* The MPcore bootloader uses these flags to start secondary CPUs.
We don't use a bootloader, so do this here. */
s->flags = 3;
......@@ -210,15 +209,28 @@ void arm_sysctl_init(uint32_t base, uint32_t sys_id)
DeviceState *dev;
dev = qdev_create(NULL, "realview_sysctl");
qdev_set_prop_int(dev, "sys_id", sys_id);
qdev_prop_set_uint32(dev, "sys_id", sys_id);
qdev_init(dev);
sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
}
static SysBusDeviceInfo arm_sysctl_info = {
.init = arm_sysctl_init1,
.qdev.name = "realview_sysctl",
.qdev.size = sizeof(arm_sysctl_state),
.qdev.props = (Property[]) {
{
.name = "sys_id",
.info = &qdev_prop_uint32,
.offset = offsetof(arm_sysctl_state, sys_id),
},
{/* end of list */}
}
};
static void arm_sysctl_register_devices(void)
{
sysbus_register_dev("realview_sysctl", sizeof(arm_sysctl_state),
arm_sysctl_init1);
sysbus_register_withprop(&arm_sysctl_info);
}
device_init(arm_sysctl_register_devices)
......@@ -127,7 +127,6 @@ static void bitband_init(SysBusDevice *dev)
BitBandState *s = FROM_SYSBUS(BitBandState, dev);
int iomemtype;
s->base = qdev_get_prop_int(&dev->qdev, "base", 0);
iomemtype = cpu_register_io_memory(bitband_readfn, bitband_writefn,
&s->base);
sysbus_init_mmio(dev, 0x02000000, iomemtype);
......@@ -138,12 +137,12 @@ static void armv7m_bitband_init(void)
DeviceState *dev;
dev = qdev_create(NULL, "ARM,bitband-memory");
qdev_set_prop_int(dev, "base", 0x20000000);
qdev_prop_set_uint32(dev, "base", 0x20000000);
qdev_init(dev);
sysbus_mmio_map(sysbus_from_qdev(dev), 0, 0x22000000);
dev = qdev_create(NULL, "ARM,bitband-memory");
qdev_set_prop_int(dev, "base", 0x40000000);
qdev_prop_set_uint32(dev, "base", 0x40000000);
qdev_init(dev);
sysbus_mmio_map(sysbus_from_qdev(dev), 0, 0x42000000);
}
......@@ -238,10 +237,23 @@ qemu_irq *armv7m_init(int flash_size, int sram_size,
return pic;
}
static SysBusDeviceInfo bitband_info = {
.init = bitband_init,
.qdev.name = "ARM,bitband-memory",
.qdev.size = sizeof(BitBandState),
.qdev.props = (Property[]) {
{
.name = "base",
.info = &qdev_prop_hex32,
.offset = offsetof(BitBandState, base),
},
{/* end of list */}
}
};
static void armv7m_register_devices(void)
{
sysbus_register_dev("ARM,bitband-memory", sizeof(BitBandState),
bitband_init);
sysbus_register_withprop(&bitband_info);
}
device_init(armv7m_register_devices)
......@@ -297,7 +297,7 @@ void axisdev88_init (ram_addr_t ram_size,
cpu_irq = cris_pic_init_cpu(env);
dev = qdev_create(NULL, "etraxfs,pic");
/* FIXME: Is there a proper way to signal vectors to the CPU core? */
qdev_set_prop_ptr(dev, "interrupt_vector", &env->interrupt_vector);
qdev_prop_set_ptr(dev, "interrupt_vector", &env->interrupt_vector);
qdev_init(dev);
s = sysbus_from_qdev(dev);
sysbus_mmio_map(s, 0, 0x3001c000);
......
......@@ -185,7 +185,7 @@ static SysBusDeviceInfo cs4231_info = {
.init = cs4231_init1,
.qdev.name = "SUNW,CS4231",
.qdev.size = sizeof(CSState),
.qdev.props = (DevicePropList[]) {
.qdev.props = (Property[]) {
{.name = NULL}
}
};
......
......@@ -321,7 +321,6 @@ static void ecc_init1(SysBusDevice *dev)
ECCState *s = FROM_SYSBUS(ECCState, dev);
sysbus_init_irq(dev, &s->irq);
s->version = qdev_get_prop_int(&dev->qdev, "version", -1);
s->regs[0] = s->version;
ecc_io_memory = cpu_register_io_memory(ecc_mem_read, ecc_mem_write, s);
sysbus_init_mmio(dev, ECC_SIZE, ecc_io_memory);
......@@ -342,7 +341,7 @@ void ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version)
SysBusDevice *s;
dev = qdev_create(NULL, "eccmemctl");
qdev_set_prop_int(dev, "version", version);
qdev_prop_set_uint32(dev, "version", version);
qdev_init(dev);
s = sysbus_from_qdev(dev);
sysbus_connect_irq(s, 0, irq);
......@@ -352,9 +351,25 @@ void ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version)
}
}
static SysBusDeviceInfo ecc_info = {
.init = ecc_init1,
.qdev.name = "eccmemctl",
.qdev.size = sizeof(ECCState),
.qdev.props = (Property[]) {
{
.name = "version",
.info = &qdev_prop_uint32,
.offset = offsetof(ECCState, version),
.defval = (uint32_t[]) { -1 },
},
{/* end of list */}
}
};
static void ecc_register_devices(void)
{
sysbus_register_dev("eccmemctl", sizeof(ECCState), ecc_init1);
sysbus_register_withprop(&ecc_info);
}
device_init(ecc_register_devices)
......@@ -120,6 +120,8 @@ struct SerialState {
struct ChannelState chn[2];
int it_shift;
int mmio_index;
uint32_t disabled;
uint32_t frequency;
};
#define SERIAL_CTRL 0
......@@ -732,13 +734,13 @@ int escc_init(target_phys_addr_t base, qemu_irq irqA, qemu_irq irqB,
SerialState *d;
dev = qdev_create(NULL, "escc");
qdev_set_prop_int(dev, "disabled", 0);
qdev_set_prop_int(dev, "frequency", clock);
qdev_set_prop_int(dev, "it_shift", it_shift);
qdev_set_prop_ptr(dev, "chrB", chrB);
qdev_set_prop_ptr(dev, "chrA", chrA);
qdev_set_prop_int(dev, "chnBtype", ser);
qdev_set_prop_int(dev, "chnAtype", ser);
qdev_prop_set_uint32(dev, "disabled", 0);
qdev_prop_set_uint32(dev, "frequency", clock);
qdev_prop_set_uint32(dev, "it_shift", it_shift);
qdev_prop_set_ptr(dev, "chrB", chrB);
qdev_prop_set_ptr(dev, "chrA", chrA);
qdev_prop_set_uint32(dev, "chnBtype", ser);
qdev_prop_set_uint32(dev, "chnAtype", ser);
qdev_init(dev);
s = sysbus_from_qdev(dev);
sysbus_connect_irq(s, 0, irqA);
......@@ -895,13 +897,13 @@ void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq,
SysBusDevice *s;
dev = qdev_create(NULL, "escc");
qdev_set_prop_int(dev, "disabled", disabled);
qdev_set_prop_int(dev, "frequency", clock);
qdev_set_prop_int(dev, "it_shift", it_shift);
qdev_set_prop_ptr(dev, "chrB", NULL);
qdev_set_prop_ptr(dev, "chrA", NULL);
qdev_set_prop_int(dev, "chnBtype", mouse);
qdev_set_prop_int(dev, "chnAtype", kbd);
qdev_prop_set_uint32(dev, "disabled", disabled);
qdev_prop_set_uint32(dev, "frequency", clock);
qdev_prop_set_uint32(dev, "it_shift", it_shift);
qdev_prop_set_ptr(dev, "chrB", NULL);
qdev_prop_set_ptr(dev, "chrA", NULL);
qdev_prop_set_uint32(dev, "chnBtype", mouse);
qdev_prop_set_uint32(dev, "chnAtype", kbd);
qdev_init(dev);
s = sysbus_from_qdev(dev);
sysbus_connect_irq(s, 0, irq);
......@@ -914,19 +916,13 @@ static void escc_init1(SysBusDevice *dev)
SerialState *s = FROM_SYSBUS(SerialState, dev);
int io;
unsigned int i;
uint32_t clock, disabled;
s->it_shift = qdev_get_prop_int(&dev->qdev, "it_shift", 0);
clock = qdev_get_prop_int(&dev->qdev, "frequency", 0);
s->chn[0].chr = qdev_get_prop_ptr(&dev->qdev, "chrB");
s->chn[1].chr = qdev_get_prop_ptr(&dev->qdev, "chrA");
disabled = qdev_get_prop_int(&dev->qdev, "disabled", 0);
s->chn[0].disabled = disabled;
s->chn[1].disabled = disabled;
s->chn[0].disabled = s->disabled;
s->chn[1].disabled = s->disabled;
for (i = 0; i < 2; i++) {
sysbus_init_irq(dev, &s->chn[i].irq);
s->chn[i].chn = 1 - i;
s->chn[i].clock = clock / 2;
s->chn[i].clock = s->frequency / 2;
if (s->chn[i].chr) {
qemu_chr_add_handlers(s->chn[i].chr, serial_can_receive,
serial_receive1, serial_event, &s->chn[i]);
......@@ -934,8 +930,6 @@ static void escc_init1(SysBusDevice *dev)
}
s->chn[0].otherchn = &s->chn[1];
s->chn[1].otherchn = &s->chn[0];
s->chn[0].type = qdev_get_prop_int(&dev->qdev, "chnBtype", 0);
s->chn[1].type = qdev_get_prop_int(&dev->qdev, "chnAtype", 0);
io = cpu_register_io_memory(escc_mem_read, escc_mem_write, s);
sysbus_init_mmio(dev, ESCC_SIZE << s->it_shift, io);
......@@ -957,15 +951,43 @@ static SysBusDeviceInfo escc_info = {
.init = escc_init1,
.qdev.name = "escc",
.qdev.size = sizeof(SerialState),
.qdev.props = (DevicePropList[]) {
{.name = "frequency", .type = PROP_TYPE_INT},
{.name = "it_shift", .type = PROP_TYPE_INT},
{.name = "disabled", .type = PROP_TYPE_INT},
{.name = "chrB", .type = PROP_TYPE_PTR},
{.name = "chrA", .type = PROP_TYPE_PTR},
{.name = "chnBtype", .type = PROP_TYPE_INT},
{.name = "chnAtype", .type = PROP_TYPE_INT},
{.name = NULL}
.qdev.props = (Property[]) {
{
.name = "frequency",
.info = &qdev_prop_uint32,
.offset = offsetof(SerialState, frequency),
},
{
.name = "it_shift",
.info = &qdev_prop_uint32,
.offset = offsetof(SerialState, it_shift),
},
{
.name = "disabled",
.info = &qdev_prop_uint32,
.offset = offsetof(SerialState, disabled),
},
{
.name = "chrB",
.info = &qdev_prop_ptr,
.offset = offsetof(SerialState, chn[1].chr),
},
{
.name = "chrA",
.info = &qdev_prop_ptr,
.offset = offsetof(SerialState, chn[0].chr),
},
{
.name = "chnBtype",
.info = &qdev_prop_uint32,
.offset = offsetof(SerialState, chn[1].type),
},
{
.name = "chnAtype",
.info = &qdev_prop_uint32,
.offset = offsetof(SerialState, chn[0].type),
},
{/* end of list */}
}
};
......
......@@ -650,12 +650,14 @@ void esp_init(target_phys_addr_t espaddr, int it_shift,
{
DeviceState *dev;
SysBusDevice *s;
ESPState *esp;
dev = qdev_create(NULL, "esp");
qdev_set_prop_ptr(dev, "dma_memory_read", dma_memory_read);
qdev_set_prop_ptr(dev, "dma_memory_write", dma_memory_write);
qdev_set_prop_ptr(dev, "dma_opaque", dma_opaque);
qdev_set_prop_int(dev, "it_shift", it_shift);
esp = DO_UPCAST(ESPState, busdev.qdev, dev);
esp->dma_memory_read = dma_memory_read;
esp->dma_memory_write = dma_memory_write;
esp->dma_opaque = dma_opaque;
esp->it_shift = it_shift;
qdev_init(dev);
s = sysbus_from_qdev(dev);
sysbus_connect_irq(s, 0, irq);
......@@ -668,11 +670,7 @@ static void esp_init1(SysBusDevice *dev)
int esp_io_memory;
sysbus_init_irq(dev, &s->irq);
s->it_shift = qdev_get_prop_int(&dev->qdev, "it_shift", -1);
assert(s->it_shift != -1);
s->dma_memory_read = qdev_get_prop_ptr(&dev->qdev, "dma_memory_read");
s->dma_memory_write = qdev_get_prop_ptr(&dev->qdev, "dma_memory_write");
s->dma_opaque = qdev_get_prop_ptr(&dev->qdev, "dma_opaque");
esp_io_memory = cpu_register_io_memory(esp_mem_read, esp_mem_write, s);
sysbus_init_mmio(dev, ESP_REGS << s->it_shift, esp_io_memory);
......
......@@ -88,7 +88,7 @@ void bareetraxfs_init (ram_addr_t ram_size,
cpu_irq = cris_pic_init_cpu(env);
dev = qdev_create(NULL, "etraxfs,pic");
/* FIXME: Is there a proper way to signal vectors to the CPU core? */
qdev_set_prop_ptr(dev, "interrupt_vector", &env->interrupt_vector);
qdev_prop_set_ptr(dev, "interrupt_vector", &env->interrupt_vector);
qdev_init(dev);
s = sysbus_from_qdev(dev);
sysbus_mmio_map(s, 0, 0x3001c000);
......
......@@ -140,7 +140,6 @@ static void etraxfs_pic_init(SysBusDevice *dev)
struct etrax_pic *s = FROM_SYSBUS(typeof (*s), dev);
int intr_vect_regs;
s->interrupt_vector = qdev_get_prop_ptr(&dev->qdev, "interrupt_vector");
qdev_init_gpio_in(&dev->qdev, irq_handler, 32);
sysbus_init_irq(dev, &s->parent_irq);
sysbus_init_irq(dev, &s->parent_nmi);
......@@ -149,10 +148,23 @@ static void etraxfs_pic_init(SysBusDevice *dev)
sysbus_init_mmio(dev, R_MAX * 4, intr_vect_regs);
}
static SysBusDeviceInfo etraxfs_pic_info = {
.init = etraxfs_pic_init,
.qdev.name = "etraxfs,pic",
.qdev.size = sizeof(struct etrax_pic),
.qdev.props = (Property[]) {
{
.name = "interrupt_vector",
.info = &qdev_prop_ptr,
.offset = offsetof(struct etrax_pic, interrupt_vector),
},
{/* end of list */}
}
};
static void etraxfs_pic_register(void)
{
sysbus_register_dev("etraxfs,pic", sizeof (struct etrax_pic),
etraxfs_pic_init);
sysbus_register_withprop(&etraxfs_pic_info);
}
device_init(etraxfs_pic_register)
......@@ -511,6 +511,8 @@ struct fdctrl_t {
/* Floppy drives */
fdrive_t drives[MAX_FD];
int reset_sensei;
uint32_t strict_io;
uint32_t mem_mapped;
};
static uint32_t fdctrl_read (void *opaque, uint32_t reg)
......@@ -1898,9 +1900,9 @@ fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped,
fdctrl_t *fdctrl;
dev = qdev_create(NULL, "fdc");
qdev_set_prop_int(dev, "strict_io", 0);
qdev_set_prop_int(dev, "mem_mapped", mem_mapped);
qdev_set_prop_int(dev, "sun4m", 0);
qdev_prop_set_uint32(dev, "strict_io", 0);
qdev_prop_set_uint32(dev, "mem_mapped", mem_mapped);
qdev_prop_set_uint32(dev, "sun4m", 0);
qdev_init(dev);
s = sysbus_from_qdev(dev);
sysbus_connect_irq(s, 0, irq);
......@@ -1931,9 +1933,9 @@ fdctrl_t *sun4m_fdctrl_init (qemu_irq irq, target_phys_addr_t io_base,
fdctrl_t *fdctrl;
dev = qdev_create(NULL, "fdc");
qdev_set_prop_int(dev, "strict_io", 1);
qdev_set_prop_int(dev, "mem_mapped", 1);
qdev_set_prop_int(dev, "sun4m", 1);
qdev_prop_set_uint32(dev, "strict_io", 1);
qdev_prop_set_uint32(dev, "mem_mapped", 1);
qdev_prop_set_uint32(dev, "sun4m", 1);
qdev_init(dev);
s = sysbus_from_qdev(dev);
sysbus_connect_irq(s, 0, irq);
......@@ -1953,7 +1955,7 @@ static void fdc_init1(SysBusDevice *dev)
sysbus_init_irq(dev, &s->irq);
qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
if (qdev_get_prop_int(&dev->qdev, "strict_io", 0)) {
if (s->strict_io) {
io = cpu_register_io_memory(fdctrl_mem_read_strict,
fdctrl_mem_write_strict, s);
} else {
......@@ -1967,12 +1969,28 @@ static SysBusDeviceInfo fdc_info = {
.init = fdc_init1,
.qdev.name = "fdc",
.qdev.size = sizeof(fdctrl_t),
.qdev.props = (DevicePropList[]) {
{.name = "io_base", .type = PROP_TYPE_INT},
{.name = "strict_io", .type = PROP_TYPE_INT},
{.name = "mem_mapped", .type = PROP_TYPE_INT},
{.name = "sun4m", .type = PROP_TYPE_INT},
{.name = NULL}
.qdev.props = (Property[]) {
{
.name = "io_base",
.info = &qdev_prop_uint32,
.offset = offsetof(fdctrl_t, io_base),
},
{
.name = "strict_io",
.info = &qdev_prop_uint32,
.offset = offsetof(fdctrl_t, strict_io),
},
{
.name = "mem_mapped",
.info = &qdev_prop_uint32,
.offset = offsetof(fdctrl_t, mem_mapped),
},
{
.name = "sun4m",
.info = &qdev_prop_uint32,
.offset = offsetof(fdctrl_t, sun4m),
},
{/* end of properties */}
}
};
......
......@@ -20,6 +20,14 @@ struct i2c_bus
static struct BusInfo i2c_bus_info = {
.name = "I2C",
.size = sizeof(i2c_bus),
.props = (Property[]) {
{
.name = "address",
.info = &qdev_prop_uint32,
.offset = offsetof(struct i2c_slave, address),
},
{/* end of list */}
}
};
static void i2c_bus_save(QEMUFile *f, void *opaque)
......@@ -151,7 +159,6 @@ static void i2c_slave_qdev_init(DeviceState *dev, DeviceInfo *base)
i2c_slave *s = I2C_SLAVE_FROM_QDEV(dev);
s->info = info;
s->address = qdev_get_prop_int(dev, "address", 0);
info->init(s);
}
......@@ -169,7 +176,7 @@ DeviceState *i2c_create_slave(i2c_bus *bus, const char *name, int addr)
DeviceState *dev;
dev = qdev_create(&bus->qbus, name);
qdev_set_prop_int(dev, "address", addr);
qdev_prop_set_uint32(dev, "address", addr);
qdev_init(dev);
return dev;
}
......@@ -40,7 +40,7 @@ struct i2c_slave
I2CSlaveInfo *info;
/* Remaining fields for internal use by the I2C code. */
int address;
uint32_t address;
};
i2c_bus *i2c_init_bus(DeviceState *parent, const char *name);
......
......@@ -17,6 +17,7 @@
typedef struct {
SysBusDevice busdev;
uint32_t memsz;
uint32_t flash_offset;
uint32_t cm_osc;
uint32_t cm_ctrl;
......@@ -230,23 +231,21 @@ static void integratorcm_init(SysBusDevice *dev)
{
int iomemtype;
integratorcm_state *s = FROM_SYSBUS(integratorcm_state, dev);
int memsz;
memsz = qdev_get_prop_int(&dev->qdev, "memsz", 0);
s->cm_osc = 0x01000048;
/* ??? What should the high bits of this value be? */
s->cm_auxosc = 0x0007feff;
s->cm_sdram = 0x00011122;
if (memsz >= 256) {
if (s->memsz >= 256) {
integrator_spd[31] = 64;
s->cm_sdram |= 0x10;
} else if (memsz >= 128) {
} else if (s->memsz >= 128) {
integrator_spd[31] = 32;
s->cm_sdram |= 0x0c;
} else if (memsz >= 64) {
} else if (s->memsz >= 64) {
integrator_spd[31] = 16;
s->cm_sdram |= 0x08;
} else if (memsz >= 32) {
} else if (s->memsz >= 32) {
integrator_spd[31] = 4;
s->cm_sdram |= 0x04;
} else {
......@@ -475,7 +474,7 @@ static void integratorcp_init(ram_addr_t ram_size,
cpu_register_physical_memory(0x80000000, ram_size, ram_offset | IO_MEM_RAM);
dev = qdev_create(NULL, "integrator_core");
qdev_set_prop_int(dev, "memsz", ram_size >> 20);
qdev_prop_set_uint32(dev, "memsz", ram_size >> 20);
qdev_init(dev);
sysbus_mmio_map((SysBusDevice *)dev, 0, 0x10000000);
......@@ -522,11 +521,24 @@ static void integratorcp_machine_init(void)
machine_init(integratorcp_machine_init);
static SysBusDeviceInfo core_info = {
.init = integratorcm_init,
.qdev.name = "integrator_core",
.qdev.size = sizeof(integratorcm_state),
.qdev.props = (Property[]) {
{
.name = "memsz",
.info = &qdev_prop_uint32,
.offset = offsetof(integratorcm_state, memsz),
},
{/* end of list */}
}
};
static void integratorcp_register_devices(void)
{
sysbus_register_dev("integrator_pic", sizeof(icp_pic_state), icp_pic_init);
sysbus_register_dev("integrator_core", sizeof(integratorcm_state),
integratorcm_init);
sysbus_register_withprop(&core_info);
}
device_init(integratorcp_register_devices)
......@@ -373,7 +373,7 @@ void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq)
IOMMUState *d;
dev = qdev_create(NULL, "iommu");
qdev_set_prop_int(dev, "version", version);
qdev_prop_set_uint32(dev, "version", version);
qdev_init(dev);
s = sysbus_from_qdev(dev);
sysbus_connect_irq(s, 0, irq);
......@@ -391,8 +391,6 @@ static void iommu_init1(SysBusDevice *dev)
sysbus_init_irq(dev, &s->irq);
s->version = qdev_get_prop_int(&dev->qdev, "version", 0);
io = cpu_register_io_memory(iommu_mem_read, iommu_mem_write, s);
sysbus_init_mmio(dev, IOMMU_NREGS * sizeof(uint32_t), io);
......@@ -405,9 +403,13 @@ static SysBusDeviceInfo iommu_info = {
.init = iommu_init1,
.qdev.name = "iommu",
.qdev.size = sizeof(IOMMUState),
.qdev.props = (DevicePropList[]) {
{.name = "version", .type = PROP_TYPE_INT},
{.name = NULL}
.qdev.props = (Property[]) {
{
.name = "version",
.info = &qdev_prop_uint32,
.offset = offsetof(IOMMUState, version),
},
{/* end of property list */}
}
};
......
......@@ -43,11 +43,11 @@
struct m48t59_t {
SysBusDevice busdev;
/* Model parameters */
int type; // 2 = m48t02, 8 = m48t08, 59 = m48t59
uint32_t type; // 2 = m48t02, 8 = m48t08, 59 = m48t59
/* Hardware parameters */
qemu_irq IRQ;
uint32_t io_base;
uint16_t size;
uint32_t size;
/* RTC management */
time_t time_offset;
time_t stop_time;
......@@ -623,9 +623,9 @@ m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr_t mem_base,
m48t59_t *d;
dev = qdev_create(NULL, "m48t59");
qdev_set_prop_int(dev, "type", type);
qdev_set_prop_int(dev, "size", size);
qdev_set_prop_int(dev, "io_base", io_base);
qdev_prop_set_uint32(dev, "type", type);
qdev_prop_set_uint32(dev, "size", size);
qdev_prop_set_uint32(dev, "io_base", io_base);
qdev_init(dev);
s = sysbus_from_qdev(dev);
sysbus_connect_irq(s, 0, IRQ);
......@@ -647,11 +647,8 @@ static void m48t59_init1(SysBusDevice *dev)
m48t59_t *s = FROM_SYSBUS(m48t59_t, dev);
int mem_index;
s->size = qdev_get_prop_int(&dev->qdev, "size", -1);
s->buffer = qemu_mallocz(s->size);
sysbus_init_irq(dev, &s->IRQ);
s->io_base = qdev_get_prop_int(&dev->qdev, "io_base", 0);
s->type = qdev_get_prop_int(&dev->qdev, "type", -1);
mem_index = cpu_register_io_memory(nvram_read, nvram_write, s);
sysbus_init_mmio(dev, s->size, mem_index);
......@@ -666,9 +663,33 @@ static void m48t59_init1(SysBusDevice *dev)
register_savevm("m48t59", -1, 1, m48t59_save, m48t59_load, s);
}
static SysBusDeviceInfo m48t59_info = {
.init = m48t59_init1,
.qdev.name = "m48t59",
.qdev.size = sizeof(m48t59_t),
.qdev.props = (Property[]) {
{
.name = "size",
.info = &qdev_prop_uint32,
.offset = offsetof(m48t59_t, size),
.defval = (uint32_t[]) { -1 },
},{
.name = "type",
.info = &qdev_prop_uint32,
.offset = offsetof(m48t59_t, type),
.defval = (uint32_t[]) { -1 },
},{
.name = "io_base",
.info = &qdev_prop_hex32,
.offset = offsetof(m48t59_t, io_base),
},
{/* end of list */}
}
};
static void m48t59_register_devices(void)
{
sysbus_register_dev("m48t59", sizeof(m48t59_t), m48t59_init1);
sysbus_register_withprop(&m48t59_info);
}
device_init(m48t59_register_devices)
......@@ -914,8 +914,8 @@ void mips_malta_init (ram_addr_t ram_size,
/* TODO: Populate SPD eeprom data. */
DeviceState *eeprom;
eeprom = qdev_create((BusState *)smbus, "smbus-eeprom");
qdev_set_prop_int(eeprom, "address", 0x50 + i);
qdev_set_prop_ptr(eeprom, "data", eeprom_buf + (i * 256));
qdev_prop_set_uint32(eeprom, "address", 0x50 + i);
qdev_prop_set_ptr(eeprom, "data", eeprom_buf + (i * 256));
qdev_init(eeprom);
}
pit = pit_init(0x40, i8259[0]);
......
......@@ -1578,7 +1578,7 @@ static void musicpal_init(ram_addr_t ram_size,
qemu_check_nic_model(&nd_table[0], "mv88w8618");
dev = qdev_create(NULL, "mv88w8618_eth");
qdev_set_netdev(dev, &nd_table[0]);
dev->nd = &nd_table[0];
qdev_init(dev);
sysbus_mmio_map(sysbus_from_qdev(dev), 0, MP_ETH_BASE);
sysbus_connect_irq(sysbus_from_qdev(dev), 0, pic[MP_ETH_IRQ]);
......
......@@ -1402,8 +1402,8 @@ static void pc_init1(ram_addr_t ram_size,
for (i = 0; i < 8; i++) {
DeviceState *eeprom;