1. 31 Oct, 2011 1 commit
    • David Gibson's avatar
      ppc: Alter CPU state to mask out TCG unimplemented instructions as appropriate · 02d4eae4
      David Gibson authored
      The CPU state contains two bitmaps, initialized from the CPU spec
      which describes which instructions are implemented on the CPU.  A
      couple of bits are defined which cover instructions (VSX and DFP)
      which are not currently implemented in TCG.  So far, these are only
      used to handle the case of -cpu host because a KVM guest can use
      the instructions when the host CPU supports them.
      However, it's a mild layering violation to simply not include those
      bits in the CPU descriptions for those CPUs that do support them,
      just because we can't handle them in TCG.  This patch corrects the
      situation, so that the instruction bits _are_ shown correctly in the
      cpu spec table, but are masked out from the cpu state in the non-KVM
      Signed-off-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
  2. 30 Oct, 2011 27 commits
    • David Gibson's avatar
      pseries: Allow writes to KVM accelerated TCE table · 74b41e56
      David Gibson authored
      Sufficiently recent kernels include a KVM call to accelerate use of
      PAPR TCE tables (IOMMU), which are used by PAPR virtual IO devices.
      This involves qemu mapping the TCE table in from a kernel obtained fd,
      which currently we do with PROT_READ only.  This is a hangover from
      early (never released) versions of this kernel interface which only
      permitted read-only mappings and required us to destroy and recreate
      the table when we needed to clear it from qemu.
      Now, the kernel permits read-write mappings, and we rely on this to
      clear the table in spapr_vio_quiesce_one().  However, due to
      insufficient testing, I forgot to update the actual mapping of the
      table in kvmppc_create_spapr_tce() to add PROT_WRITE to the mmap().
      This patch corrects the oversight.
      Signed-off-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
    • Alexander Graf's avatar
      KVM: PPC: Override host vmx/vsx/dfp only when information known · 70bca53f
      Alexander Graf authored
      The -cpu host feature tries to find out the host capabilities based
      on device tree information. However, we don't always have that available
      because it's an optional property in dt.
      So instead of force unsetting values depending on an unreliable source
      of information, let's just try to be clever about it and not override
      capabilities when we don't know the device tree pieces.
      This fixes altivec with -cpu host on YDL PowerStations.
      Reported-by: default avatarNishanth Aravamudan <nacc@us.ibm.com>
      Acked-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
    • David Gibson's avatar
      ppc: Fix up usermode only builds · 98efaf75
      David Gibson authored
      The recent usage of MemoryRegion in kvm_ppc.h breaks builds with
      CONFIG_USER_ONLY=y.  This patch fixes it.
      Signed-off-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
    • David Gibson's avatar
      pseries: Correct vmx/dfp handling in both KVM and TCG cases · a7342588
      David Gibson authored
      Currently, when KVM is enabled, the pseries machine checks if the host
      CPU supports VMX, VSX and/or DFP instructions and advertises
      accordingly in the guest device tree.  It does this regardless of what
      CPU is selected on the command line.  On the other hand, when in TCG
      mode, it never advertises any of these facilities, even basic VMX
      (Altivec) which is supported in TCG.
      Now that we have a -cpu host option for ppc, it is fairly
      straightforward to fix both problems.  This patch changes the -cpu
      host code to override the basic cpu spec derived from the PVR with
      information queried from the host avout VMX, VSX and DFP capability.
      The pseries code then uses the instruction availability advertised in
      the cpu state to set the guest device tree correctly for both the KVM
      and TCG cases.
      Signed-off-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
    • Alexander Graf's avatar
      PPC: Fail configure when libfdt is not available · f90a9d02
      Alexander Graf authored
      We have several targets in the PPC tree now that basically require libfdt
      to function properly, namely the pseries and the e500 targets. This dependency
      will rather increase than decrease in the future, so I want to make sure
      that people building shiny new 1.0 actually have libfdt installed to get
      rid of a few ifdefs in the code.
      Warning: This patch will likely make configure fail for people who don't
      select their own --target-list, but don't have libfdt development packages
      installed. However, we really need this new dependency to move on.
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      v1 -> v2:
        - no paranthesis
        - no fdt check for config_pseries
        - add . in error message
    • David Gibson's avatar
      ppc: Avoid decrementer related kvm exits · 55f7d4b0
      David Gibson authored
      In __cpu_ppc_store_decr(), we set up a regular timer used to trigger
      decrementer interrupts.  This is necessary to implement the decrementer
      properly under TCG, but is unnecessary under KVM (true for both Book3S-PR
      and Book3S-HV KVM variants), because the kernel handles generating and
      delivering decrementer exceptions.
      Under kvm, in fact, the timer causes expensive and unnecessary exits from
      kvm to qemu.  This patch, therefore, disables setting the timer when kvm
      is in use.
      Signed-off-by: default avatarAnton Blanchard <anton@au1.ibm.com>
      Signed-off-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
    • Alexander Graf's avatar
      PPC: Disable non-440 CPUs for ppcemb target · f0ad8c34
      Alexander Graf authored
      The sole reason we have the ppcemb target is to support MMUs that have
      less than the usual 4k possible page size. There are very few of these
      chips and I don't want to add additional QA and testing burden to everyone
      to ensure that code still works when TARGET_PAGE_SIZE is not 4k.
      So this patch disables all CPUs except for MMU_BOOKE capable ones from
      the ppcemb target.
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
    • Alexander Graf's avatar
      PPC: Bump qemu-system-ppc to 64-bit physical address space · 8b242eba
      Alexander Graf authored
      Some 32-bit PPC CPUs can use up to 36 bit of physical address space.
      Treat them accordingly in the qemu-system-ppc binary type.
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
    • David Gibson's avatar
      pseries: Under kvm use guest cpu = host cpu by default · 6b7a2cf6
      David Gibson authored
      Now that we've implemented -cpu host for ppc, this patch updates the
      pseries machine to use the host cpu as the guest cpu by default when
      running under KVM.  This is important because under KVM Book3S-HV the guest
      cpu _cannot_ be of a different type to the host cpu (at the moment
      KVM Book3S-HV will silently virtualize the host cpu instead of whatever was
      requested, but in future it is likely to simply refuse to run the VM if
      a cpu model other than the host's is requested).
      Signed-off-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
    • David Gibson's avatar
      ppc: Add cpu defs for POWER7 revisions 2.1 and 2.3 · 37e305ce
      David Gibson authored
      This patch adds cpu specs to the table for POWER7 revisions 2.1 and 2.3.
      This allows -cpu host to be used on these host cpus.
      Signed-off-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
    • David Gibson's avatar
      ppc: First cut implementation of -cpu host · a1e98583
      David Gibson authored
      For convenience with kvm, x86 allows the user to specify -cpu host on the
      qemu command line, which means make the guest cpu the same as the host
      cpu.  This patch implements the same option for ppc targets.
      For now, this just read the host PVR (Processor Version Register) and
      selects one of our existing CPU specs based on it.  This means that the
      option will not work if the host cpu is not supported by TCG, even if that
      wouldn't matter for use under kvm.
      In future, we can extend this in future to override parts of the cpu spec
      based on information obtained from the host (via /proc/cpuinfo, the host
      device tree, or explicit KVM calls).  That will let us handle cases where
      the real kvm-virtualized CPU doesn't behave exactly like the TCG-emulated
      CPU.  With appropriate annotation of the CPU specs we'll also then be able
      to use host cpus under kvm even when there isn't a matching full TCG model.
      Signed-off-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
    • David Gibson's avatar
      ppc: Remove broken partial PVR matching · be40edcd
      David Gibson authored
      The ppc target contains a ppc_find_by_pvr() function, which looks up a
      CPU spec based on a PVR (that is, based on the value in the target cpu's
      Processor Version Register).  PVR values contain information on both the
      cpu model (upper 16 bits, usually) and on the precise revision (low 16
      bits, usually).
      ppc_find_by_pvr, as well as making exact PVR matches, attempts to find
      "close" PVR matches, when we don't have a CPU spec for the exact revision
      specified.  This sounds like a good idea, execpt that the current logic
      is completely nonsensical.
      It seems to assume CPU families are subdivided bit by bit in the PVR in a
      way they just aren't.  Specifically, it requires a match on all bits of the
      specified pvr up to the last non-zero bit.  This has the bizarre effect
      that when the low bits are simply a sequential revision number (a common
      though not universal pattern), then odd specified revisions must be matched
      exactly, whereas even specified revisions will also match the next odd
      revision, likewise for powers of 4, 8 and so forth.
      To correctly do inexact matching we'd need to re-organize the table of CPU
      specs to include a mask showing what PVR range the spec is compatible with
      (similar to the cputable code in the Linux kernel).
      For now, just remove the bogosity by only permitting exact PVR matches.
      That at least makes the matching simple and consistent.  If we need inexact
      matching we can add the necessary per-subfamily masks later.
      Signed-off-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
    • David Gibson's avatar
      pseries: Update SLOF firmware image · d20dfdd4
      David Gibson authored
      This patch is a general update to the SLOF firmware image used on the
      pseries machine.  This doesn't contain updates for specific features but
      contains a number of bugfixes and enhancements in the main SLOF tree from
      Thomas Huth.
      Signed-off-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
    • David Gibson's avatar
      pseries: Add device tree properties for VMX/VSX and DFP under kvm · 6659394f
      David Gibson authored
      Sufficiently recent PAPR specifications define properties "ibm,vmx"
      and "ibm,dfp" on the CPU node which advertise whether the VMX vector
      extensions (or the later VSX version) and/or the Decimal Floating
      Point operations from IBM's recent POWER CPUs are available.
      Currently we do not put these in the guest device tree and the guest
      kernel will consequently assume they are not available.  This is good,
      because they are not supported under TCG.  VMX is similar enough to
      Altivec that it might be trivial to support, but VSX and DFP would
      both require significant work to support in TCG.
      However, when running under kvm on a host which supports these
      instructions, there's no reason not to let the guest use them.  This
      patch, therefore, checks for the relevant support on the host CPU
      and, if present, advertises them to the guest as well.
      Signed-off-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
    • David Gibson's avatar
      ppc: Generalize the kvmppc_get_clockfreq() function · 9bc884b7
      David Gibson authored
      Currently the kvmppc_get_clockfreq() function reads the host's clock
      frequency from /proc/device-tree, which is useful to past to the guest
      in KVM setups.  However, there are some other host properties
      advertised in the device tree which can also be relevant to the
      This patch, therefore, replaces kvmppc_get_clockfreq() which can
      retrieve any named, single integer property from the host device
      tree's CPU node.
      Signed-off-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
    • Fabien Chouteau's avatar
      Set an invalid-bits mask for each SPE instructions · 70560da7
      Fabien Chouteau authored
      SPE instructions are defined by pairs. Currently, the invalid-bits mask is set
      for the first instruction, but the second one can have a different mask.
      GEN_SPE(efdcmpeq,    efdcfs,      0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
      Signed-off-by: default avatarFabien Chouteau <chouteau@adacore.com>
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
    • David Gibson's avatar
      pseries: Update SLOF firmware image · bdcf9d6c
      David Gibson authored
      This patch updates the SLOF submodule and precompiled image.  The new
      SLOF versions contains two changes of note:
       * The previous SLOF has a bug in SCSI condition handling that was
         exposed by recent updates to qemu's SCSI emulation.  This update
         fixes the bug.
       * The previous SLOF has a bug in its addressing of SCSI devices,
         which can be exposed under certain conditions.  The new SLOF also
         fixes this.
      Signed-off-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
    • David Gibson's avatar
      pseries: Use Book3S-HV TCE acceleration capabilities · 0f5cb298
      David Gibson authored
      The pseries machine of qemu implements the TCE mechanism used as a
      virtual IOMMU for the PAPR defined virtual IO devices.  Because the
      PAPR spec only defines a small DMA address space, the guest VIO
      drivers need to update TCE mappings very frequently - the virtual
      network device is particularly bad.  This means many slow exits to
      qemu to emulate the H_PUT_TCE hypercall.
      Sufficiently recent kernels allow this to be mitigated by implementing
      H_PUT_TCE in the host kernel.  To make use of this, however, qemu
      needs to initialize the necessary TCE tables, and map them into itself
      so that the VIO device implementations can retrieve the mappings when
      they access guest memory (which is treated as a virtual DMA
      This patch adds the necessary calls to use the KVM TCE acceleration.
      If the kernel does not support acceleration, or there is some other
      error creating the accelerated TCE table, then it will still fall back
      to full userspace TCE implementation.
      Signed-off-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
    • David Gibson's avatar
      pseries: Allow KVM Book3S-HV on PPC970 CPUS · 354ac20a
      David Gibson authored
      At present, using the hypervisor aware Book3S-HV KVM will only work
      with qemu on POWER7 CPUs.  PPC970 CPUs also have hypervisor
      capability, but they lack the VRMA feature which makes assigning guest
      memory easier.
      In order to allow KVM Book3S-HV on PPC970, we need to specially
      allocate the first chunk of guest memory (the "Real Mode Area" or
      RMA), so that it is physically contiguous.
      Sufficiently recent host kernels allow such contiguous RMAs to be
      allocated, with a kvm capability advertising whether the feature is
      available and/or necessary on this hardware.  This patch enables qemu
      to use this support, thus allowing kvm acceleration of pseries qemu
      machines on PPC970 hardware.
      Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      Signed-off-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      agraf: fix to use memory api
    • David Gibson's avatar
      pseries: Support SMT systems for KVM Book3S-HV · e97c3636
      David Gibson authored
      Alex Graf has already made qemu support KVM for the pseries machine
      when using the Book3S-PR KVM variant (which runs the guest in
      usermode, emulating supervisor operations).  This code allows gets us
      very close to also working with KVM Book3S-HV (using the hypervisor
      capabilities of recent POWER CPUs).
      This patch moves us another step towards Book3S-HV support by
      correctly handling SMT (multithreaded) POWER CPUs.  There are two
      parts to this:
       * Querying KVM to check SMT capability, and if present, adjusting the
         cpu numbers that qemu assigns to cause KVM to assign guest threads
         to cores in the right way (this isn't automatic, because the POWER
         HV support has a limitation that different threads on a single core
         cannot be in different guests at the same time).
       * Correctly informing the guest OS of the SMT thread to core mappings
         via the device tree.
      Signed-off-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
    • Liu Yu-B13201's avatar
      ppc/e500_pci: Fix an array overflow issue · eeae2e7b
      Liu Yu-B13201 authored
      When access PPCE500_PCI_IW1 the previous index get overflow.
      The patch fix the issue and update all to keep consistent style.
      Signed-off-by: default avatarLiu Yu <yu.liu@freescale.com>
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
    • Liu Yu-B13201's avatar
      ppc/e500_pci: Fix code style · 6875dc8e
      Liu Yu-B13201 authored
      Put trailing statements on next line.
      Signed-off-by: default avatarLiu Yu <yu.liu@freescale.com>
      Reviewed-by: default avatarAndreas Färber <andreas.faerber@web.de>
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
    • Max Filippov's avatar
    • Richard Henderson's avatar
      tcg: Optimize some forms of deposit. · df072774
      Richard Henderson authored
      If the deposit replaces the entire word, optimize to a move.
      If we're inserting to the top of the word, avoid the mask of arg2
      as we'll be shifting out all of the garbage and shifting in zeros.
      If the host is 32-bit, reduce a 64-bit deposit to a 32-bit deposit
      when possible.
      Signed-off-by: default avatarRichard Henderson <rth@twiddle.net>
      Signed-off-by: default avatarBlue Swirl <blauwirbel@gmail.com>
    • Aneesh Kumar K.V's avatar
      hw/9pfs: Make VirtFS tracing work correctly · 7999f7e1
      Aneesh Kumar K.V authored
      this patch fix multiple issues with VirtFS tracing.
      a) Add tracepoint to the correct code path. We handle error in complete_pdu
      b) Fix indentation in python script
      c) Fix variable naming issue in python script
      Signed-off-by: default avatarAneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
      Signed-off-by: default avatarBlue Swirl <blauwirbel@gmail.com>
    • Stefan Weil's avatar
      exec-all: Fix void pointer arithmetic · c2f36c6c
      Stefan Weil authored
      Adding an offset to a void pointer works with gcc but is not allowed
      by the current C standards. With -pedantic, gcc complains:
      exec-all.h:344: error: pointer of type ‘void *’ used in arithmetic
      Fix this, and also replace (unsigned long) by (uintptr_t) in the same
      Signed-off-by: default avatarStefan Weil <sw@weilnetz.de>
      Signed-off-by: default avatarBlue Swirl <blauwirbel@gmail.com>
    • David Gibson's avatar
      Add linux-headers/asm to .gitignore · d787fcf4
      David Gibson authored
      linux-headers/asm is a symlink generated during configure.  It should not,
      therefore be committed to git, nor show up in git diffs and the like.
      Signed-off-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
      Reviewed-by: default avatarJuan Quintela <quintela@redhat.com>
      Signed-off-by: default avatarBlue Swirl <blauwirbel@gmail.com>
  3. 27 Oct, 2011 1 commit
    • Blue Swirl's avatar
      Merge branch 'rth/vis2' of git://repo.or.cz/qemu/rth · b5a12aa2
      Blue Swirl authored
      * 'rth/vis2' of git://repo.or.cz/qemu/rth:
        target-sparc: Implement FALIGNDATA inline.
        target-sparc: Implement BMASK/BSHUFFLE.
        target-sparc: Implement ALIGNADDR* inline.
        target-sparc: Implement EDGE* instructions.
        target-sparc: Implement fpack{16,32,fix}.
        target-sparc: Implement PDIST.
        target-sparc: Do exceptions management fully inside the helpers.
        target-sparc: Change fpr representation to doubles.
        target-sparc: Undo cpu_fpr rename.
        target-sparc: Extract float128 move to a function.
        target-sparc: Extract common code for floating-point operations.
        target-sparc: Make FPU/VIS helpers const when possible.
        target-sparc: Pass float64 parameters instead of dt0/1 temporaries.
        target-sparc: Add accessors for double-precision fpr access.
        target-sparc: Mark fprs dirty in store accessor.
        target-sparc: Add accessors for single-precision fpr access.
  4. 26 Oct, 2011 11 commits