1. 16 Jul, 2009 10 commits
  2. 15 Jul, 2009 5 commits
  3. 13 Jul, 2009 2 commits
  4. 12 Jul, 2009 17 commits
    • Baojun Wang's avatar
      target-ppc: enable PPC_MFTB for 44x · f4078236
      Baojun Wang authored
      
      
      According to PPC440 user manual, PPC 440 supports ``mftb'' even it's a
      preserved instruction:
      
      PPC440_UM2013.pdf, p.445, table A-3
      
      when I compile a kernel (2.6.30, bamboo_defconfig/440EP &
      canyonlands/460EX), I can see ``mftb'' by using ppc-xxx-objdump
      vmlinux
      
      I have also checked the ppc 440x[456], 460S, 464, they also should support mftb.
      
      The following patch enable mftb for all ppc 440 variants, including:
      440EP, 440GP, 440x4, 440x5 and 460
      Signed-off-by: default avatarBaojun Wang <wangbj@gmail.com>
      Signed-off-by: default avatarAurelien Jarno <aurelien@aurel32.net>
      f4078236
    • Baojun Wang's avatar
      ppc tcg: fix wrong bit/mask of wrteei · fbe73008
      Baojun Wang authored
      
      Signed-off-by: default avatarBaojun Wang <wangbj@gmail.com>
      Signed-off-by: default avatarAurelien Jarno <aurelien@aurel32.net>
      fbe73008
    • Nathan Froyd's avatar
      gdb-xml: fix hacks in powerpc register numbering · 22555301
      Nathan Froyd authored
      
      
      The powerpc xml files contained a hack--an empty, non-existent
      register--for getting the register numbers to line up for
      newer (XML-aware) and older (non-XML-aware) GDB.  While this hack worked
      in some cases, it didn't work in all cases, notably when the user used
      `finish' or `continue': GDB would attempt to read the non-existent
      register and QEMU would complain.
      
      This patch fixes things up properly.  Instead of inserting a fake
      register, we explicitly declare the floating-point and SPE registers to
      start at 71.  This action accomplishes the same thing as the nasty hack,
      except that now GDB never tries to fetch the non-existant register 70.
      Signed-off-by: default avatarNathan Froyd <froydnj@codesourcery.com>
      Signed-off-by: default avatarAurelien Jarno <aurelien@aurel32.net>
      22555301
    • Nathan Froyd's avatar
      target-ppc: fix evmergelo and evmergelohi · 33890b3e
      Nathan Froyd authored
      
      
      For 32-bit PPC targets, we translated:
      
      evmergelo rX, rX, rY
      
      as:
      
      rX-lo = rY-lo
      rX-hi = rX-lo
      
      which is wrong, because we should be transferring rX-lo first.  This
      problem is fixed by swapping the order in which we write the parts of
      rX.
      
      Similarly, we translated:
      
      evmergelohi rX, rX, rY
      
      as:
      
      rX-lo = rY-hi
      rX-hi = rX-lo
      
      In this case, we can't swap the assignment statements, because that
      would just cause problems for:
      
      evmergelohi rX, rY, rX
      
      Instead, we detect the first case and save rX-lo in a temporary
      variable:
      
      tmp = rX-lo
      rX-lo = rY-hi
      rX-hi = tmp
      
      These problems don't occur on PPC64 targets because we don't split the
      SPE registers into hi/lo parts for such targets.
      Signed-off-by: default avatarNathan Froyd <froydnj@codesourcery.com>
      Signed-off-by: default avatarAurelien Jarno <aurelien@aurel32.net>
      33890b3e
    • Tristan Gingold's avatar
      target-ppc: fix typo in _cpu_ppc_load_decr · f55e9d9a
      Tristan Gingold authored
      
      
      Use parameter 'next' to fix the hdecr case.
      Also pass 'next' by value instead of pointer (more easy to read and no
      performance issue for an always_inline function).
      Signed-off-by: default avatarTristan Gingold <gingold@adacore.com>
      Signed-off-by: default avatarAurelien Jarno <aurelien@aurel32.net>
      f55e9d9a
    • Blue Swirl's avatar
      Sparc32/Sparc64/PPC: convert m48txx to qdev · d27cf0ae
      Blue Swirl authored
      
      Signed-off-by: default avatarBlue Swirl <blauwirbel@gmail.com>
      d27cf0ae
    • Blue Swirl's avatar
      Sparc32: convert tcx to qdev · f40070c3
      Blue Swirl authored
      
      
      Also increase QDEV_MAX_MMIO.
      Signed-off-by: default avatarBlue Swirl <blauwirbel@gmail.com>
      f40070c3
    • Blue Swirl's avatar
      Sparc32: use the OpenFirmware name for ecc · 798b721e
      Blue Swirl authored
      
      Signed-off-by: default avatarBlue Swirl <blauwirbel@gmail.com>
      798b721e
    • Aurelien Jarno's avatar
      344b983d
    • Paul Brook's avatar
      Fix MIPS SC · feeb3b6a
      Paul Brook authored
      
      
      Fix botched merge of op_ldst_sc calls to match actual implementation.
      Thanks to Aurelien Jarno for diagnosing this.
      Signed-off-by: default avatarPaul Brook <paul@codesourcery.com>
      feeb3b6a
    • Blue Swirl's avatar
      Sparc64: convert ebus to qdev · 53e3c4f9
      Blue Swirl authored
      
      Signed-off-by: default avatarBlue Swirl <blauwirbel@gmail.com>
      53e3c4f9
    • Igor Kovalenko's avatar
      sparc64: trap handling corrections · 5210977a
      Igor Kovalenko authored
      On Sun, Jul 12, 2009 at 12:09 PM, Blue Swirl<blauwirbel@gmail.com> wrote:
      > On 7/12/09, Igor Kovalenko <igor.v.kovalenko@gmail.com> wrote:
      >> Good trap handling is required to process interrupts.
      >>  This patch fixes the following:
      >>
      >>  - sparc64 has no wim register
      >>  - sparc64 has no psret register, use IE bit of pstate
      >>   extract IE checking code to cpu_interrupts_enabled
      >>  - alternate globals are not available if cpu has GL feature
      >>   in this case bit AG of pstate is constant zero
      >>  - write to pstate must actually write pstate
      >>   even if cpu has GL feature
      >>
      >>  Also timer interrupt is handled using do_interrupt.
      >
      > A bit too much for one patch. Please also remove the code instead of
      > commenting out.
      
      I now excluded timer interrupt related part.
      To my mind other changes are essentially tied together.
      
      > PUT_PSR for Sparc64 needs CC_OP = CC_OP_FLAGS; like Sparc32.
      
      Fixed, please find attached the updated version.
      
      --
      Kind regards,
      Igor V. Kovalenko
      5210977a
    • Blue Swirl's avatar
      Sparc32: convert eccmemctl to qdev · 49e66373
      Blue Swirl authored
      
      Signed-off-by: default avatarBlue Swirl <blauwirbel@gmail.com>
      49e66373
    • Igor Kovalenko's avatar
      sparc64: fix helper_st_asi little endian case typo · 5b0f0bec
      Igor Kovalenko authored
      On Sun, Jul 12, 2009 at 12:43 AM, Stuart Brady<sdbrady@ntlworld.com> wrote:
      > On Sat, Jul 11, 2009 at 10:22:18PM +0400, Igor Kovalenko wrote:
      >> It is clear that intention is to byte-swap value to be written, not
      >> the target address.
      >
      > @@ -1949,13 +1949,13 @@ void helper_st_asi(target_ulong addr, ta
      >     case 0x89: // Secondary LE
      >         switch(size) {
      >         case 2:
      > -            addr = bswap16(addr);
      > +            addr = bswap16(val);
      >             ^^^^
      > Shouldn't that be 'val = bswap16(val)' (and likewise for the 32-bit and
      > 64-bit cases)?  Also needs a 'signed-off-by:'...
      >
      > Cheers,
      > --
      > Stuart Brady
      >
      
      Thanks, that part I did not runtime-tested.
      Not sure if those asi stores are of any use for user-mode emulator.
      
      Please find attached the corrected version.
      
      Signed-off-by: igor.v.kovalenko@gmail.com
      
      --
      Kind regards,
      Igor V. Kovalenko
      5b0f0bec
    • Igor Kovalenko's avatar
      sparc64: really initialize irq · 7d55273f
      Igor Kovalenko authored
      Allocate irq just before passing it to pci bridge initialization
      and actually use it to initialize pci bridge.
      
      Signed-off-by: igor.v.kovalenko@gmail.com
      
      --
      Kind regards,
      Igor V. Kovalenko
      7d55273f
    • Igor Kovalenko's avatar
      sparc64: unify mmu tag matching code · 536ba015
      Igor Kovalenko authored
      This patch extracts common part of sparc64 tag
      matching code used by IMMU and DMMU lookups.
      
      Signed-off-by: igor.v.kovalenko@gmail.com
      
      --
      Kind regards,
      Igor V. Kovalenko
      536ba015
    • Igor Kovalenko's avatar
      sparc64: mmu bypass mode correction · e8807b14
      Igor Kovalenko authored
      This Implement physical address truncation in mmu bypass mode.
      IMMU bypass is also active when cpu enters RED_STATE
      
      Signed-off-by: igor.v.kovalenko@gmail.com
      
      --
      Kind regards,
      Igor V. Kovalenko
      e8807b14
  5. 11 Jul, 2009 3 commits
  6. 10 Jul, 2009 3 commits