1. 16 Jul, 2009 29 commits
  2. 15 Jul, 2009 5 commits
  3. 13 Jul, 2009 2 commits
  4. 12 Jul, 2009 4 commits
    • Baojun Wang's avatar
      target-ppc: enable PPC_MFTB for 44x · f4078236
      Baojun Wang authored
      
      
      According to PPC440 user manual, PPC 440 supports ``mftb'' even it's a
      preserved instruction:
      
      PPC440_UM2013.pdf, p.445, table A-3
      
      when I compile a kernel (2.6.30, bamboo_defconfig/440EP &
      canyonlands/460EX), I can see ``mftb'' by using ppc-xxx-objdump
      vmlinux
      
      I have also checked the ppc 440x[456], 460S, 464, they also should support mftb.
      
      The following patch enable mftb for all ppc 440 variants, including:
      440EP, 440GP, 440x4, 440x5 and 460
      Signed-off-by: default avatarBaojun Wang <wangbj@gmail.com>
      Signed-off-by: default avatarAurelien Jarno <aurelien@aurel32.net>
      f4078236
    • Baojun Wang's avatar
      ppc tcg: fix wrong bit/mask of wrteei · fbe73008
      Baojun Wang authored
      
      Signed-off-by: default avatarBaojun Wang <wangbj@gmail.com>
      Signed-off-by: default avatarAurelien Jarno <aurelien@aurel32.net>
      fbe73008
    • Nathan Froyd's avatar
      gdb-xml: fix hacks in powerpc register numbering · 22555301
      Nathan Froyd authored
      
      
      The powerpc xml files contained a hack--an empty, non-existent
      register--for getting the register numbers to line up for
      newer (XML-aware) and older (non-XML-aware) GDB.  While this hack worked
      in some cases, it didn't work in all cases, notably when the user used
      `finish' or `continue': GDB would attempt to read the non-existent
      register and QEMU would complain.
      
      This patch fixes things up properly.  Instead of inserting a fake
      register, we explicitly declare the floating-point and SPE registers to
      start at 71.  This action accomplishes the same thing as the nasty hack,
      except that now GDB never tries to fetch the non-existant register 70.
      Signed-off-by: default avatarNathan Froyd <froydnj@codesourcery.com>
      Signed-off-by: default avatarAurelien Jarno <aurelien@aurel32.net>
      22555301
    • Nathan Froyd's avatar
      target-ppc: fix evmergelo and evmergelohi · 33890b3e
      Nathan Froyd authored
      
      
      For 32-bit PPC targets, we translated:
      
      evmergelo rX, rX, rY
      
      as:
      
      rX-lo = rY-lo
      rX-hi = rX-lo
      
      which is wrong, because we should be transferring rX-lo first.  This
      problem is fixed by swapping the order in which we write the parts of
      rX.
      
      Similarly, we translated:
      
      evmergelohi rX, rX, rY
      
      as:
      
      rX-lo = rY-hi
      rX-hi = rX-lo
      
      In this case, we can't swap the assignment statements, because that
      would just cause problems for:
      
      evmergelohi rX, rY, rX
      
      Instead, we detect the first case and save rX-lo in a temporary
      variable:
      
      tmp = rX-lo
      rX-lo = rY-hi
      rX-hi = tmp
      
      These problems don't occur on PPC64 targets because we don't split the
      SPE registers into hi/lo parts for such targets.
      Signed-off-by: default avatarNathan Froyd <froydnj@codesourcery.com>
      Signed-off-by: default avatarAurelien Jarno <aurelien@aurel32.net>
      33890b3e