• Peter Maydell's avatar
    Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180301' into staging · 9db0855e
    Peter Maydell authored
    
    
    target-arm queue:
     * update MAINTAINERS for Alistair's new email address
     * add Arm v8.2 FP16 arithmetic extension for linux-user
     * implement display connector emulation for vexpress board
     * xilinx_spips: Enable only two slaves when reading/writing with stripe
     * xilinx_spips: Use 8 dummy cycles with the QIOR/QIOR4 commands
     * hw: register: Run post_write hook on reset
    
    # gpg: Signature made Thu 01 Mar 2018 11:22:46 GMT
    # gpg:                using RSA key 3C2525ED14360CDE
    # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
    # gpg:                 aka "Peter Maydell <pmaydell@gmail.com>"
    # gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
    # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE
    
    * remotes/pmaydell/tags/pull-target-arm-20180301: (42 commits)
      MAINTAINERS: Update my email address
      linux-user: Report AArch64 FP16 support via hwcap bits
      target/arm: Enable ARM_V8_FP16 feature bit for the AArch64 "any" CPU
      arm/translate-a64: add all single op FP16 to handle_fp_1src_half
      arm/translate-a64: implement simd_scalar_three_reg_same_fp16
      arm/translate-a64: add all FP16 ops in simd_scalar_pairwise
      arm/translate-a64: add FP16 FMOV to simd_mod_imm
      arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16
      arm/helper.c: re-factor rsqrte and add rsqrte_f16
      arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16
      arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16
      arm/translate-a64: add FP16 FRECPE
      arm/helper.c: re-factor recpe and add recepe_f16
      arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16
      arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16
      arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16
      arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16
      arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16
      arm/translate-a64: initial decode for simd_two_reg_misc_fp16
      arm/translate-a64: add FP16 x2 ops for simd_indexed
      ...
    
    Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
    9db0855e