Commit 2a221651 authored by Edgar E. Iglesias's avatar Edgar E. Iglesias

exec: Make cpu_physical_memory_write_rom input an AS

Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: default avatarEdgar E. Iglesias <edgar.iglesias@xilinx.com>
parent db3be60d
...@@ -2102,7 +2102,7 @@ enum write_rom_type { ...@@ -2102,7 +2102,7 @@ enum write_rom_type {
FLUSH_CACHE, FLUSH_CACHE,
}; };
static inline void cpu_physical_memory_write_rom_internal( static inline void cpu_physical_memory_write_rom_internal(AddressSpace *as,
hwaddr addr, const uint8_t *buf, int len, enum write_rom_type type) hwaddr addr, const uint8_t *buf, int len, enum write_rom_type type)
{ {
hwaddr l; hwaddr l;
...@@ -2112,8 +2112,7 @@ static inline void cpu_physical_memory_write_rom_internal( ...@@ -2112,8 +2112,7 @@ static inline void cpu_physical_memory_write_rom_internal(
while (len > 0) { while (len > 0) {
l = len; l = len;
mr = address_space_translate(&address_space_memory, mr = address_space_translate(as, addr, &addr1, &l, true);
addr, &addr1, &l, true);
if (!(memory_region_is_ram(mr) || if (!(memory_region_is_ram(mr) ||
memory_region_is_romd(mr))) { memory_region_is_romd(mr))) {
...@@ -2139,10 +2138,10 @@ static inline void cpu_physical_memory_write_rom_internal( ...@@ -2139,10 +2138,10 @@ static inline void cpu_physical_memory_write_rom_internal(
} }
/* used for ROM loading : can write in RAM and ROM */ /* used for ROM loading : can write in RAM and ROM */
void cpu_physical_memory_write_rom(hwaddr addr, void cpu_physical_memory_write_rom(AddressSpace *as, hwaddr addr,
const uint8_t *buf, int len) const uint8_t *buf, int len)
{ {
cpu_physical_memory_write_rom_internal(addr, buf, len, WRITE_DATA); cpu_physical_memory_write_rom_internal(as, addr, buf, len, WRITE_DATA);
} }
void cpu_flush_icache_range(hwaddr start, int len) void cpu_flush_icache_range(hwaddr start, int len)
...@@ -2157,7 +2156,8 @@ void cpu_flush_icache_range(hwaddr start, int len) ...@@ -2157,7 +2156,8 @@ void cpu_flush_icache_range(hwaddr start, int len)
return; return;
} }
cpu_physical_memory_write_rom_internal(start, NULL, len, FLUSH_CACHE); cpu_physical_memory_write_rom_internal(&address_space_memory,
start, NULL, len, FLUSH_CACHE);
} }
typedef struct { typedef struct {
...@@ -2721,7 +2721,8 @@ int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr, ...@@ -2721,7 +2721,8 @@ int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
l = len; l = len;
phys_addr += (addr & ~TARGET_PAGE_MASK); phys_addr += (addr & ~TARGET_PAGE_MASK);
if (is_write) if (is_write)
cpu_physical_memory_write_rom(phys_addr, buf, l); cpu_physical_memory_write_rom(&address_space_memory,
phys_addr, buf, l);
else else
cpu_physical_memory_rw(phys_addr, buf, l, is_write); cpu_physical_memory_rw(phys_addr, buf, l, is_write);
len -= l; len -= l;
......
...@@ -778,7 +778,8 @@ static void rom_reset(void *unused) ...@@ -778,7 +778,8 @@ static void rom_reset(void *unused)
void *host = memory_region_get_ram_ptr(rom->mr); void *host = memory_region_get_ram_ptr(rom->mr);
memcpy(host, rom->data, rom->datasize); memcpy(host, rom->data, rom->datasize);
} else { } else {
cpu_physical_memory_write_rom(rom->addr, rom->data, rom->datasize); cpu_physical_memory_write_rom(&address_space_memory,
rom->addr, rom->data, rom->datasize);
} }
if (rom->isrom) { if (rom->isrom) {
/* rom needs to be written only once */ /* rom needs to be written only once */
......
...@@ -129,7 +129,8 @@ static void apic_sync_vapic(APICCommonState *s, int sync_type) ...@@ -129,7 +129,8 @@ static void apic_sync_vapic(APICCommonState *s, int sync_type)
} }
vapic_state.irr = vector & 0xff; vapic_state.irr = vector & 0xff;
cpu_physical_memory_write_rom(s->vapic_paddr + start, cpu_physical_memory_write_rom(&address_space_memory,
s->vapic_paddr + start,
((void *)&vapic_state) + start, length); ((void *)&vapic_state) + start, length);
} }
} }
......
...@@ -577,7 +577,8 @@ static void idreg_init(hwaddr addr) ...@@ -577,7 +577,8 @@ static void idreg_init(hwaddr addr)
s = SYS_BUS_DEVICE(dev); s = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(s, 0, addr); sysbus_mmio_map(s, 0, addr);
cpu_physical_memory_write_rom(addr, idreg_data, sizeof(idreg_data)); cpu_physical_memory_write_rom(&address_space_memory,
addr, idreg_data, sizeof(idreg_data));
} }
#define MACIO_ID_REGISTER(obj) \ #define MACIO_ID_REGISTER(obj) \
......
...@@ -108,7 +108,7 @@ void stl_phys(AddressSpace *as, hwaddr addr, uint32_t val); ...@@ -108,7 +108,7 @@ void stl_phys(AddressSpace *as, hwaddr addr, uint32_t val);
void stq_phys(AddressSpace *as, hwaddr addr, uint64_t val); void stq_phys(AddressSpace *as, hwaddr addr, uint64_t val);
#endif #endif
void cpu_physical_memory_write_rom(hwaddr addr, void cpu_physical_memory_write_rom(AddressSpace *as, hwaddr addr,
const uint8_t *buf, int len); const uint8_t *buf, int len);
void cpu_flush_icache_range(hwaddr start, int len); void cpu_flush_icache_range(hwaddr start, int len);
......
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