Commit 986a2998 authored by Andreas Färber's avatar Andreas Färber

gdbstub: Replace GET_REG*() macros with gdb_get_reg*() functions

This avoids polluting the global namespace with a non-prefixed macro and
makes it obvious in the call sites that we return.

Semi-automatic conversion using, e.g.,
 sed -i 's/GET_REGL(/return gdb_get_regl(mem_buf, /g' target-*/gdbstub.c
followed by manual tweaking for sparc's GET_REGA() and Coding Style.

Acked-by: Michael Walle <michael@walle.cc> (for lm32)
Acked-by: Max Filippov <jcmvbkbc@gmail.com> (for xtensa)
Signed-off-by: default avatarAndreas Färber <afaerber@suse.de>
parent 25d8ac0e
......@@ -489,35 +489,6 @@ static int put_packet(GDBState *s, const char *buf)
return put_packet_binary(s, buf, strlen(buf));
}
/* The GDB remote protocol transfers values in target byte order. This means
we can use the raw memory access routines to access the value buffer.
Conveniently, these also handle the case where the buffer is mis-aligned.
*/
#define GET_REG8(val) do { \
stb_p(mem_buf, val); \
return 1; \
} while(0)
#define GET_REG16(val) do { \
stw_p(mem_buf, val); \
return 2; \
} while(0)
#define GET_REG32(val) do { \
stl_p(mem_buf, val); \
return 4; \
} while(0)
#define GET_REG64(val) do { \
stq_p(mem_buf, val); \
return 8; \
} while(0)
#if TARGET_LONG_BITS == 64
#define GET_REGL(val) GET_REG64(val)
#define ldtul_p(addr) ldq_p(addr)
#else
#define GET_REGL(val) GET_REG32(val)
#define ldtul_p(addr) ldl_p(addr)
#endif
#if defined(TARGET_I386)
#include "target-i386/gdbstub.c"
......
......@@ -39,6 +39,43 @@ static inline int cpu_index(CPUState *cpu)
#endif
}
/* The GDB remote protocol transfers values in target byte order. This means
* we can use the raw memory access routines to access the value buffer.
* Conveniently, these also handle the case where the buffer is mis-aligned.
*/
static inline int gdb_get_reg8(uint8_t *mem_buf, uint8_t val)
{
stb_p(mem_buf, val);
return 1;
}
static inline int gdb_get_reg16(uint8_t *mem_buf, uint16_t val)
{
stw_p(mem_buf, val);
return 2;
}
static inline int gdb_get_reg32(uint8_t *mem_buf, uint32_t val)
{
stl_p(mem_buf, val);
return 4;
}
static inline int gdb_get_reg64(uint8_t *mem_buf, uint64_t val)
{
stq_p(mem_buf, val);
return 8;
}
#if TARGET_LONG_BITS == 64
#define gdb_get_regl(buf, val) gdb_get_reg64(buf, val)
#define ldtul_p(addr) ldq_p(addr)
#else
#define gdb_get_regl(buf, val) gdb_get_reg32(buf, val)
#define ldtul_p(addr) ldl_p(addr)
#endif
#endif
#ifdef CONFIG_USER_ONLY
......
......@@ -49,7 +49,7 @@ static int cpu_gdb_read_register(CPUAlphaState *env, uint8_t *mem_buf, int n)
default:
return 0;
}
GET_REGL(val);
return gdb_get_regl(mem_buf, val);
}
static int cpu_gdb_write_register(CPUAlphaState *env, uint8_t *mem_buf, int n)
......
......@@ -28,7 +28,7 @@ static int cpu_gdb_read_register(CPUARMState *env, uint8_t *mem_buf, int n)
{
if (n < 16) {
/* Core integer register. */
GET_REG32(env->regs[n]);
return gdb_get_reg32(mem_buf, env->regs[n]);
}
if (n < 24) {
/* FPA registers. */
......@@ -44,10 +44,10 @@ static int cpu_gdb_read_register(CPUARMState *env, uint8_t *mem_buf, int n)
if (gdb_has_xml) {
return 0;
}
GET_REG32(0);
return gdb_get_reg32(mem_buf, 0);
case 25:
/* CPSR */
GET_REG32(cpsr_read(env));
return gdb_get_reg32(mem_buf, cpsr_read(env));
}
/* Unknown register. */
return 0;
......
......@@ -22,25 +22,25 @@ static int
read_register_crisv10(CPUCRISState *env, uint8_t *mem_buf, int n)
{
if (n < 15) {
GET_REG32(env->regs[n]);
return gdb_get_reg32(mem_buf, env->regs[n]);
}
if (n == 15) {
GET_REG32(env->pc);
return gdb_get_reg32(mem_buf, env->pc);
}
if (n < 32) {
switch (n) {
case 16:
GET_REG8(env->pregs[n - 16]);
return gdb_get_reg8(mem_buf, env->pregs[n - 16]);
case 17:
GET_REG8(env->pregs[n - 16]);
return gdb_get_reg8(mem_buf, env->pregs[n - 16]);
case 20:
case 21:
GET_REG16(env->pregs[n - 16]);
return gdb_get_reg16(mem_buf, env->pregs[n - 16]);
default:
if (n >= 23) {
GET_REG32(env->pregs[n - 16]);
return gdb_get_reg32(mem_buf, env->pregs[n - 16]);
}
break;
}
......@@ -58,28 +58,28 @@ static int cpu_gdb_read_register(CPUCRISState *env, uint8_t *mem_buf, int n)
srs = env->pregs[PR_SRS];
if (n < 16) {
GET_REG32(env->regs[n]);
return gdb_get_reg32(mem_buf, env->regs[n]);
}
if (n >= 21 && n < 32) {
GET_REG32(env->pregs[n - 16]);
return gdb_get_reg32(mem_buf, env->pregs[n - 16]);
}
if (n >= 33 && n < 49) {
GET_REG32(env->sregs[srs][n - 33]);
return gdb_get_reg32(mem_buf, env->sregs[srs][n - 33]);
}
switch (n) {
case 16:
GET_REG8(env->pregs[0]);
return gdb_get_reg8(mem_buf, env->pregs[0]);
case 17:
GET_REG8(env->pregs[1]);
return gdb_get_reg8(mem_buf, env->pregs[1]);
case 18:
GET_REG32(env->pregs[2]);
return gdb_get_reg32(mem_buf, env->pregs[2]);
case 19:
GET_REG8(srs);
return gdb_get_reg8(mem_buf, srs);
case 20:
GET_REG16(env->pregs[4]);
return gdb_get_reg16(mem_buf, env->pregs[4]);
case 32:
GET_REG32(env->pc);
return gdb_get_reg32(mem_buf, env->pc);
}
return 0;
......
......@@ -39,9 +39,9 @@ static int cpu_gdb_read_register(CPUX86State *env, uint8_t *mem_buf, int n)
{
if (n < CPU_NB_REGS) {
if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
GET_REG64(env->regs[gpr_map[n]]);
return gdb_get_reg64(mem_buf, env->regs[gpr_map[n]]);
} else if (n < CPU_NB_REGS32) {
GET_REG32(env->regs[gpr_map32[n]]);
return gdb_get_reg32(mem_buf, env->regs[gpr_map32[n]]);
}
} else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) {
#ifdef USE_X86LDOUBLE
......@@ -63,46 +63,46 @@ static int cpu_gdb_read_register(CPUX86State *env, uint8_t *mem_buf, int n)
switch (n) {
case IDX_IP_REG:
if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
GET_REG64(env->eip);
return gdb_get_reg64(mem_buf, env->eip);
} else {
GET_REG32(env->eip);
return gdb_get_reg32(mem_buf, env->eip);
}
case IDX_FLAGS_REG:
GET_REG32(env->eflags);
return gdb_get_reg32(mem_buf, env->eflags);
case IDX_SEG_REGS:
GET_REG32(env->segs[R_CS].selector);
return gdb_get_reg32(mem_buf, env->segs[R_CS].selector);
case IDX_SEG_REGS + 1:
GET_REG32(env->segs[R_SS].selector);
return gdb_get_reg32(mem_buf, env->segs[R_SS].selector);
case IDX_SEG_REGS + 2:
GET_REG32(env->segs[R_DS].selector);
return gdb_get_reg32(mem_buf, env->segs[R_DS].selector);
case IDX_SEG_REGS + 3:
GET_REG32(env->segs[R_ES].selector);
return gdb_get_reg32(mem_buf, env->segs[R_ES].selector);
case IDX_SEG_REGS + 4:
GET_REG32(env->segs[R_FS].selector);
return gdb_get_reg32(mem_buf, env->segs[R_FS].selector);
case IDX_SEG_REGS + 5:
GET_REG32(env->segs[R_GS].selector);
return gdb_get_reg32(mem_buf, env->segs[R_GS].selector);
case IDX_FP_REGS + 8:
GET_REG32(env->fpuc);
return gdb_get_reg32(mem_buf, env->fpuc);
case IDX_FP_REGS + 9:
GET_REG32((env->fpus & ~0x3800) |
(env->fpstt & 0x7) << 11);
return gdb_get_reg32(mem_buf, (env->fpus & ~0x3800) |
(env->fpstt & 0x7) << 11);
case IDX_FP_REGS + 10:
GET_REG32(0); /* ftag */
return gdb_get_reg32(mem_buf, 0); /* ftag */
case IDX_FP_REGS + 11:
GET_REG32(0); /* fiseg */
return gdb_get_reg32(mem_buf, 0); /* fiseg */
case IDX_FP_REGS + 12:
GET_REG32(0); /* fioff */
return gdb_get_reg32(mem_buf, 0); /* fioff */
case IDX_FP_REGS + 13:
GET_REG32(0); /* foseg */
return gdb_get_reg32(mem_buf, 0); /* foseg */
case IDX_FP_REGS + 14:
GET_REG32(0); /* fooff */
return gdb_get_reg32(mem_buf, 0); /* fooff */
case IDX_FP_REGS + 15:
GET_REG32(0); /* fop */
return gdb_get_reg32(mem_buf, 0); /* fop */
case IDX_MXCSR_REG:
GET_REG32(env->mxcsr);
return gdb_get_reg32(mem_buf, env->mxcsr);
}
}
return 0;
......
......@@ -22,24 +22,24 @@
static int cpu_gdb_read_register(CPULM32State *env, uint8_t *mem_buf, int n)
{
if (n < 32) {
GET_REG32(env->regs[n]);
return gdb_get_reg32(mem_buf, env->regs[n]);
} else {
switch (n) {
case 32:
GET_REG32(env->pc);
return gdb_get_reg32(mem_buf, env->pc);
/* FIXME: put in right exception ID */
case 33:
GET_REG32(0);
return gdb_get_reg32(mem_buf, 0);
case 34:
GET_REG32(env->eba);
return gdb_get_reg32(mem_buf, env->eba);
case 35:
GET_REG32(env->deba);
return gdb_get_reg32(mem_buf, env->deba);
case 36:
GET_REG32(env->ie);
return gdb_get_reg32(mem_buf, env->ie);
case 37:
GET_REG32(lm32_pic_get_im(env->pic_state));
return gdb_get_reg32(mem_buf, lm32_pic_get_im(env->pic_state));
case 38:
GET_REG32(lm32_pic_get_ip(env->pic_state));
return gdb_get_reg32(mem_buf, lm32_pic_get_ip(env->pic_state));
}
}
return 0;
......
......@@ -22,16 +22,16 @@ static int cpu_gdb_read_register(CPUM68KState *env, uint8_t *mem_buf, int n)
{
if (n < 8) {
/* D0-D7 */
GET_REG32(env->dregs[n]);
return gdb_get_reg32(mem_buf, env->dregs[n]);
} else if (n < 16) {
/* A0-A7 */
GET_REG32(env->aregs[n - 8]);
return gdb_get_reg32(mem_buf, env->aregs[n - 8]);
} else {
switch (n) {
case 16:
GET_REG32(env->sr);
return gdb_get_reg32(mem_buf, env->sr);
case 17:
GET_REG32(env->pc);
return gdb_get_reg32(mem_buf, env->pc);
}
}
/* FP registers not included here because they vary between
......
......@@ -21,9 +21,9 @@
static int cpu_gdb_read_register(CPUMBState *env, uint8_t *mem_buf, int n)
{
if (n < 32) {
GET_REG32(env->regs[n]);
return gdb_get_reg32(mem_buf, env->regs[n]);
} else {
GET_REG32(env->sregs[n - 32]);
return gdb_get_reg32(mem_buf, env->sregs[n - 32]);
}
return 0;
}
......
......@@ -21,44 +21,47 @@
static int cpu_gdb_read_register(CPUMIPSState *env, uint8_t *mem_buf, int n)
{
if (n < 32) {
GET_REGL(env->active_tc.gpr[n]);
return gdb_get_regl(mem_buf, env->active_tc.gpr[n]);
}
if (env->CP0_Config1 & (1 << CP0C1_FP)) {
if (n >= 38 && n < 70) {
if (env->CP0_Status & (1 << CP0St_FR)) {
GET_REGL(env->active_fpu.fpr[n - 38].d);
return gdb_get_regl(mem_buf,
env->active_fpu.fpr[n - 38].d);
} else {
GET_REGL(env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX]);
return gdb_get_regl(mem_buf,
env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX]);
}
}
switch (n) {
case 70:
GET_REGL((int32_t)env->active_fpu.fcr31);
return gdb_get_regl(mem_buf, (int32_t)env->active_fpu.fcr31);
case 71:
GET_REGL((int32_t)env->active_fpu.fcr0);
return gdb_get_regl(mem_buf, (int32_t)env->active_fpu.fcr0);
}
}
switch (n) {
case 32:
GET_REGL((int32_t)env->CP0_Status);
return gdb_get_regl(mem_buf, (int32_t)env->CP0_Status);
case 33:
GET_REGL(env->active_tc.LO[0]);
return gdb_get_regl(mem_buf, env->active_tc.LO[0]);
case 34:
GET_REGL(env->active_tc.HI[0]);
return gdb_get_regl(mem_buf, env->active_tc.HI[0]);
case 35:
GET_REGL(env->CP0_BadVAddr);
return gdb_get_regl(mem_buf, env->CP0_BadVAddr);
case 36:
GET_REGL((int32_t)env->CP0_Cause);
return gdb_get_regl(mem_buf, (int32_t)env->CP0_Cause);
case 37:
GET_REGL(env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16));
return gdb_get_regl(mem_buf, env->active_tc.PC |
!!(env->hflags & MIPS_HFLAG_M16));
case 72:
GET_REGL(0); /* fp */
return gdb_get_regl(mem_buf, 0); /* fp */
case 89:
GET_REGL((int32_t)env->CP0_PRid);
return gdb_get_regl(mem_buf, (int32_t)env->CP0_PRid);
}
if (n >= 73 && n <= 88) {
/* 16 embedded regs. */
GET_REGL(0);
return gdb_get_regl(mem_buf, 0);
}
return 0;
......
......@@ -21,17 +21,17 @@
static int cpu_gdb_read_register(CPUOpenRISCState *env, uint8_t *mem_buf, int n)
{
if (n < 32) {
GET_REG32(env->gpr[n]);
return gdb_get_reg32(mem_buf, env->gpr[n]);
} else {
switch (n) {
case 32: /* PPC */
GET_REG32(env->ppc);
return gdb_get_reg32(mem_buf, env->ppc);
case 33: /* NPC */
GET_REG32(env->npc);
return gdb_get_reg32(mem_buf, env->npc);
case 34: /* SR */
GET_REG32(env->sr);
return gdb_get_reg32(mem_buf, env->sr);
default:
break;
......
......@@ -29,7 +29,7 @@ static int cpu_gdb_read_register(CPUPPCState *env, uint8_t *mem_buf, int n)
{
if (n < 32) {
/* gprs */
GET_REGL(env->gpr[n]);
return gdb_get_regl(mem_buf, env->gpr[n]);
} else if (n < 64) {
/* fprs */
if (gdb_has_xml) {
......@@ -40,9 +40,9 @@ static int cpu_gdb_read_register(CPUPPCState *env, uint8_t *mem_buf, int n)
} else {
switch (n) {
case 64:
GET_REGL(env->nip);
return gdb_get_regl(mem_buf, env->nip);
case 65:
GET_REGL(env->msr);
return gdb_get_regl(mem_buf, env->msr);
case 66:
{
uint32_t cr = 0;
......@@ -50,20 +50,20 @@ static int cpu_gdb_read_register(CPUPPCState *env, uint8_t *mem_buf, int n)
for (i = 0; i < 8; i++) {
cr |= env->crf[i] << (32 - ((i + 1) * 4));
}
GET_REG32(cr);
return gdb_get_reg32(mem_buf, cr);
}
case 67:
GET_REGL(env->lr);
return gdb_get_regl(mem_buf, env->lr);
case 68:
GET_REGL(env->ctr);
return gdb_get_regl(mem_buf, env->ctr);
case 69:
GET_REGL(env->xer);
return gdb_get_regl(mem_buf, env->xer);
case 70:
{
if (gdb_has_xml) {
return 0;
}
GET_REG32(env->fpscr);
return gdb_get_reg32(mem_buf, env->fpscr);
}
}
}
......
......@@ -27,17 +27,17 @@ static int cpu_gdb_read_register(CPUS390XState *env, uint8_t *mem_buf, int n)
case S390_PSWM_REGNUM:
cc_op = calc_cc(env, env->cc_op, env->cc_src, env->cc_dst, env->cc_vr);
val = deposit64(env->psw.mask, 44, 2, cc_op);
GET_REGL(val);
return gdb_get_regl(mem_buf, val);
case S390_PSWA_REGNUM:
GET_REGL(env->psw.addr);
return gdb_get_regl(mem_buf, env->psw.addr);
case S390_R0_REGNUM ... S390_R15_REGNUM:
GET_REGL(env->regs[n-S390_R0_REGNUM]);
return gdb_get_regl(mem_buf, env->regs[n-S390_R0_REGNUM]);
case S390_A0_REGNUM ... S390_A15_REGNUM:
GET_REG32(env->aregs[n-S390_A0_REGNUM]);
return gdb_get_reg32(mem_buf, env->aregs[n-S390_A0_REGNUM]);
case S390_FPC_REGNUM:
GET_REG32(env->fpc);
return gdb_get_reg32(mem_buf, env->fpc);
case S390_F0_REGNUM ... S390_F15_REGNUM:
GET_REG64(env->fregs[n-S390_F0_REGNUM].ll);
return gdb_get_reg64(mem_buf, env->fregs[n-S390_F0_REGNUM].ll);
}
return 0;
......
......@@ -26,30 +26,30 @@ static int cpu_gdb_read_register(CPUSH4State *env, uint8_t *mem_buf, int n)
switch (n) {
case 0 ... 7:
if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
GET_REGL(env->gregs[n + 16]);
return gdb_get_regl(mem_buf, env->gregs[n + 16]);
} else {
GET_REGL(env->gregs[n]);
return gdb_get_regl(mem_buf, env->gregs[n]);
}
case 8 ... 15:
GET_REGL(env->gregs[n]);
return gdb_get_regl(mem_buf, env->gregs[n]);
case 16:
GET_REGL(env->pc);
return gdb_get_regl(mem_buf, env->pc);
case 17:
GET_REGL(env->pr);
return gdb_get_regl(mem_buf, env->pr);
case 18:
GET_REGL(env->gbr);
return gdb_get_regl(mem_buf, env->gbr);
case 19:
GET_REGL(env->vbr);
return gdb_get_regl(mem_buf, env->vbr);
case 20:
GET_REGL(env->mach);
return gdb_get_regl(mem_buf, env->mach);
case 21:
GET_REGL(env->macl);
return gdb_get_regl(mem_buf, env->macl);
case 22:
GET_REGL(env->sr);
return gdb_get_regl(mem_buf, env->sr);
case 23:
GET_REGL(env->fpul);
return gdb_get_regl(mem_buf, env->fpul);
case 24:
GET_REGL(env->fpscr);
return gdb_get_regl(mem_buf, env->fpscr);
case 25 ... 40:
if (env->fpscr & FPSCR_FR) {
stfl_p(mem_buf, env->fregs[n - 9]);
......@@ -58,13 +58,13 @@ static int cpu_gdb_read_register(CPUSH4State *env, uint8_t *mem_buf, int n)
}
return 4;
case 41:
GET_REGL(env->ssr);
return gdb_get_regl(mem_buf, env->ssr);
case 42:
GET_REGL(env->spc);
return gdb_get_regl(mem_buf, env->spc);
case 43 ... 50:
GET_REGL(env->gregs[n - 43]);
return gdb_get_regl(mem_buf, env->gregs[n - 43]);
case 51 ... 58:
GET_REGL(env->gregs[n - (51 - 16)]);
return gdb_get_regl(mem_buf, env->gregs[n - (51 - 16)]);
}
return 0;
......
......@@ -19,80 +19,80 @@
*/
#ifdef TARGET_ABI32
#define GET_REGA(val) GET_REG32(val)
#define gdb_get_rega(buf, val) gdb_get_reg32(buf, val)
#else
#define GET_REGA(val) GET_REGL(val)
#define gdb_get_rega(buf, val) gdb_get_regl(buf, val)
#endif
static int cpu_gdb_read_register(CPUSPARCState *env, uint8_t *mem_buf, int n)
{
if (n < 8) {
/* g0..g7 */
GET_REGA(env->gregs[n]);
return gdb_get_rega(mem_buf, env->gregs[n]);
}
if (n < 32) {
/* register window */
GET_REGA(env->regwptr[n - 8]);
return gdb_get_rega(mem_buf, env->regwptr[n - 8]);
}
#if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)
if (n < 64) {
/* fprs */
if (n & 1) {
GET_REG32(env->fpr[(n - 32) / 2].l.lower);
return gdb_get_reg32(mem_buf, env->fpr[(n - 32) / 2].l.lower);
} else {
GET_REG32(env->fpr[(n - 32) / 2].l.upper);
return gdb_get_reg32(mem_buf, env->fpr[(n - 32) / 2].l.upper);
}
}
/* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
switch (n) {
case 64:
GET_REGA(env->y);
return gdb_get_rega(mem_buf, env->y);
case 65:
GET_REGA(cpu_get_psr(env));
return gdb_get_rega(mem_buf, cpu_get_psr(env));
case 66:
GET_REGA(env->wim);
return gdb_get_rega(mem_buf, env->wim);
case 67:
GET_REGA(env->tbr);
return gdb_get_rega(mem_buf, env->tbr);
case 68:
GET_REGA(env->pc);
return gdb_get_rega(mem_buf, env->pc);
case 69:
GET_REGA(env->npc);
return gdb_get_rega(mem_buf, env->npc);
case 70:
GET_REGA(env->fsr);
return gdb_get_rega(mem_buf, env->fsr);
case 71:
GET_REGA(0); /* csr */
return gdb_get_rega(mem_buf, 0); /* csr */
default:
GET_REGA(0);
return gdb_get_rega(mem_buf, 0);
}
#else
if (n < 64) {
/* f0-f31 */
if (n & 1) {
GET_REG32(env->fpr[(n - 32) / 2].l.lower);
return gdb_get_reg32(mem_buf, env->fpr[(n - 32) / 2].l.lower);
} else {
GET_REG32(env->fpr[(n - 32) / 2].l.upper);
return gdb_get_reg32(mem_buf, env->fpr[(n - 32) / 2].l.upper);
}
}
if (n < 80) {
/* f32-f62 (double width, even numbers only) */
GET_REG64(env->fpr[(n - 32) / 2].ll);
return gdb_get_reg64(mem_buf, env->fpr[(n - 32) / 2].ll);
}
switch (n) {
case 80:
GET_REGL(env->pc);
return gdb_get_regl(mem_buf, env->pc);
case 81:
GET_REGL(env->npc);
return gdb_get_regl(mem_buf, env->npc);
case 82:
GET_REGL((cpu_get_ccr(env) << 32) |
((env->asi & 0xff) << 24) |
((env->pstate & 0xfff) << 8) |
cpu_get_cwp64(env));
return gdb_get_regl(mem_buf, (cpu_get_ccr(env) << 32) |
((env->asi & 0xff) << 24) |
((env->pstate & 0xfff) << 8) |
cpu_get_cwp64(env));
case 83:
GET_REGL(env->fsr);
return gdb_get_regl(mem_buf, env->fsr);
case 84:
GET_REGL(env->fprs);
return gdb_get_regl(mem_buf, env->fprs);
case 85:
GET_REGL(env->y);
return gdb_get_regl(mem_buf, env->y);
}
#endif
return 0;
......
......@@ -28,23 +28,25 @@ static int cpu_gdb_read_register(CPUXtensaState *env, uint8_t *mem_buf, int n)
switch (reg->type) {
case 9: /*pc*/
GET_REG32(env->pc);
return gdb_get_reg32(mem_buf, env->pc);
case 1: /*ar*/
xtensa_sync_phys_from_window(env);
GET_REG32(env->phys_regs[(reg->targno & 0xff) % env->config->nareg]);
return gdb_get_reg32(mem_buf, env->phys_regs[(reg->targno & 0xff)
% env->config->nareg]);
case 2: /*SR*/
GET_REG32(env->sregs[reg->targno & 0xff]);
return gdb_get_reg32(mem_buf, env->sregs[reg->targno & 0xff]);
case 3: /*UR*/
GET_REG32(env->uregs[reg->targno & 0xff]);
return gdb_get_reg32(mem_buf, env->uregs[reg->targno & 0xff]);
case 4: /*f*/
GET_REG32(float32_val(env->fregs[reg->targno & 0x0f]));
return gdb_get_reg32(mem_buf, float32_val(env->fregs[reg->targno
& 0x0f]));
case 8: /*a*/
GET_REG32(env->regs[reg->targno & 0x0f]);
return gdb_get_reg32(mem_buf, env->regs[reg->targno & 0x0f]);
default:
qemu_log("%s from reg %d of unsupported type %d\n",
......
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