1. 24 May, 2018 1 commit
  2. 14 Jul, 2017 1 commit
  3. 21 Jun, 2017 1 commit
  4. 07 Jun, 2017 1 commit
    • Abdallah Bouassida's avatar
      target/i386: Add GDB XML description for SSE registers · b8158192
      Abdallah Bouassida authored
      Add an XML description for SSE registers (XMM+MXCSR) for both X86
      and X86-64 architectures in the GDB stub:
      - configure: Define gdb_xml_files for the X86 targets (32 and 64bit).
      - gdb-xml/i386-32bit-sse.xml & gdb-xml/i386-64bit-sse.xml: The XML files
      that contain a description of the XMM + MXCSR registers.
      - gdb-xml/i386-32bit.xml & gdb-xml/i386-64bit.xml: wrappers that include
      the XML file of the core registers and the other XML file of the SSE registers.
      - target/i386/cpu.c: Modify the gdb_core_xml_file to the new XML wrapper,
        modify the gdb_num_core_regs to fit the registers number defined in each
        XML file.
      Signed-off-by: 's avatarAbdallah Bouassida <abdallah.bouassida@lauterbach.com>
      Signed-off-by: 's avatarPaolo Bonzini <pbonzini@redhat.com>
      b8158192
  5. 05 May, 2017 1 commit
    • Abdallah Bouassida's avatar
      target/i386: Add GDB XML register description support · 00fcd100
      Abdallah Bouassida authored
      This patch implements XML target description support for X86 and X86-64
      architectures in the GDB stub, as the way with ARM and PowerPC:
      - gdb-xml/32bit-core.xml & gdb-xml/64bit-core.xml: Adding the XML target
        description files, these files are picked from GDB source code.
      - configure: Define gdb_xml_files for X86 targets.
      - target/i386/cpu.c: Define gdb_core_xml_file and gdb_arch_name to add
        XML awareness for this architecture, modify the gdb_num_core_regs to
        fit the registers number defined in each XML file.
      Signed-off-by: 's avatarAbdallah Bouassida <abdallah.bouassida@lauterbach.com>
      Message-Id: <2b3c8119-1602-28c7-eab4-296593877103@lauterbach.com>
      Signed-off-by: 's avatarPaolo Bonzini <pbonzini@redhat.com>
      00fcd100
  6. 30 Jan, 2016 1 commit
  7. 02 Oct, 2015 1 commit
  8. 07 Sep, 2015 1 commit
  9. 27 May, 2015 1 commit
  10. 01 Sep, 2014 1 commit
  11. 17 Dec, 2013 1 commit
  12. 10 Sep, 2013 1 commit
  13. 12 Jul, 2009 1 commit
    • Nathan Froyd's avatar
      gdb-xml: fix hacks in powerpc register numbering · 22555301
      Nathan Froyd authored
      The powerpc xml files contained a hack--an empty, non-existent
      register--for getting the register numbers to line up for
      newer (XML-aware) and older (non-XML-aware) GDB.  While this hack worked
      in some cases, it didn't work in all cases, notably when the user used
      `finish' or `continue': GDB would attempt to read the non-existent
      register and QEMU would complain.
      
      This patch fixes things up properly.  Instead of inserting a fake
      register, we explicitly declare the floating-point and SPE registers to
      start at 71.  This action accomplishes the same thing as the nasty hack,
      except that now GDB never tries to fetch the non-existant register 70.
      Signed-off-by: 's avatarNathan Froyd <froydnj@codesourcery.com>
      Signed-off-by: 's avatarAurelien Jarno <aurelien@aurel32.net>
      22555301
  14. 07 Mar, 2009 1 commit
    • aurel32's avatar
      Work around QEMU GDB stub suboptimality · d2c75345
      aurel32 authored
      The current XML files claim, on floating point-supporting Power chips,
      that $f0 is register 70.  This would be fine, except that register 70
      for non-XML-aware GDB is FPSCR.  More importantly, 70 is less than
      NUM_CORE_REGS (71) for Power, so a request for register 70 goes to the
      "core" register reading routines, rather than the floating-point
      register read routine we registered with gdb_register_coprocessor.
      
      Therefore, when we are talking to an XML-aware GDB, we claim that
      register has zero width, which causes the rest of QEMU's GDB stub to
      send an error back to GDB, which causes GDB to be unable to read the
      floating-point registers.  (The problem is also present for SPE
      registers and occurs in a slightly different way for Altivec registers.)
      
      The best way to fix this is to have the "core register" XML files for
      PPC32 and PPC64 claim that there is a 4-byte register 70, which causes
      $f0 to be register 71, and everything works just fine from that point
      forward.
      Signed-off-by: 's avatarNathan Froyd <froydnj@codesourcery.com>
      Signed-off-by: 's avatarAurelien Jarno <aurelien@aurel32.net>
      
      git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6770 c046a42c-6fe2-441c-8c8c-71466251a162
      d2c75345
  15. 04 Mar, 2009 1 commit
  16. 24 Jan, 2009 1 commit
  17. 11 Oct, 2008 1 commit