1. 24 May, 2018 1 commit
  2. 12 Jul, 2009 1 commit
    • Nathan Froyd's avatar
      gdb-xml: fix hacks in powerpc register numbering · 22555301
      Nathan Froyd authored
      The powerpc xml files contained a hack--an empty, non-existent
      register--for getting the register numbers to line up for
      newer (XML-aware) and older (non-XML-aware) GDB.  While this hack worked
      in some cases, it didn't work in all cases, notably when the user used
      `finish' or `continue': GDB would attempt to read the non-existent
      register and QEMU would complain.
      This patch fixes things up properly.  Instead of inserting a fake
      register, we explicitly declare the floating-point and SPE registers to
      start at 71.  This action accomplishes the same thing as the nasty hack,
      except that now GDB never tries to fetch the non-existant register 70.
      Signed-off-by: default avatarNathan Froyd <froydnj@codesourcery.com>
      Signed-off-by: default avatarAurelien Jarno <aurelien@aurel32.net>
  3. 07 Mar, 2009 1 commit
    • aurel32's avatar
      Work around QEMU GDB stub suboptimality · d2c75345
      aurel32 authored
      The current XML files claim, on floating point-supporting Power chips,
      that $f0 is register 70.  This would be fine, except that register 70
      for non-XML-aware GDB is FPSCR.  More importantly, 70 is less than
      NUM_CORE_REGS (71) for Power, so a request for register 70 goes to the
      "core" register reading routines, rather than the floating-point
      register read routine we registered with gdb_register_coprocessor.
      Therefore, when we are talking to an XML-aware GDB, we claim that
      register has zero width, which causes the rest of QEMU's GDB stub to
      send an error back to GDB, which causes GDB to be unable to read the
      floating-point registers.  (The problem is also present for SPE
      registers and occurs in a slightly different way for Altivec registers.)
      The best way to fix this is to have the "core register" XML files for
      PPC32 and PPC64 claim that there is a 4-byte register 70, which causes
      $f0 to be register 71, and everything works just fine from that point
      Signed-off-by: default avatarNathan Froyd <froydnj@codesourcery.com>
      Signed-off-by: default avatarAurelien Jarno <aurelien@aurel32.net>
      git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6770 c046a42c-6fe2-441c-8c8c-71466251a162
  4. 24 Jan, 2009 1 commit