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Angus Ainslie
angus.ainslie
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Eric Kuzmenko
eric.kuzmenko
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Evangelos Ribeiro Tzaras
evangelos.tzaras
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Francois Techene
francois.techene
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Guido Gunther
guido.gunther
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JC Staudt
jcstaudt
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Jonathon Hall
jonathon.hall
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Julian Sparber
julian.sparber
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Martin Kepplinger
martin.kepplinger
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Mohammed Sadiq
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Sam Hewitt sam.hewitt
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Sebastian Krzyszkowiak
sebastian.krzyszkowiak
- Oct 19, 2020
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Sebastian Krzyszkowiak authoredDocument changes and release 20.1.10-1pureos+librem5.1 See merge request Librem5/mesa!8
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Guido Gunther authoredUpdate to 20.1.10 See merge request Librem5/mesa!7
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- Oct 18, 2020
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Sebastian Krzyszkowiak authored
Drop patch numbers, rename, move Purism patches into separate directory.
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- Oct 17, 2020
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Sebastian Krzyszkowiak authored
It's broken on GC7000L and leads to incorrect rendering results.
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Sebastian Krzyszkowiak authored
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Sebastian Krzyszkowiak authored
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Sebastian Krzyszkowiak authored
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- Oct 14, 2020
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Eric Engestrom authored
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Tony Wasserka authored
AMD ISA docs explicitly require this for VS, and this likely extends to NGG too. Cc: mesa-stable Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3615 Reviewed-by:
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Bas Nieuwenhuizen authored
With arrays we really have to use the correct size for the base mipmap to get the right array pitch. In particular, using surf_pitch results in pitch that is bigger than the base mipmap and hence results in wrong pitches computed by the HW. It seems that on GFX9 this has mostly been hidden by the epitch provided in the descriptor but this is not something we do on GFX10 anymore. Now this has some draw-backs: 1. normalized coordinates don't work 2. Bounds checking uses slightly bigger bounds. 2 mostly is not an issue as we still ensure that they're within the texture memory and not overlapping other layers/mips, but we can't properly ignore writes. 1 is kinda dead in the water ... On the other hand I'd argue that using normalized coords & a filter for sampling a block view of a compressed format is extraordinarily useless. The old method we employed already had these drawbacks for everything except the base miplevel of the imageview. AFAICT this is the same tradeoff AMDVLK makes and no CTS test hits this. (once it does I think the HW is dead in the water ... Only workaround I can think of is shader processing which is hard because we don't know texture formats at compile time.) I also removed the extra calculations when the image has only 1 mip level because they ended up being a no-op in that case. CC: mesa-stable Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2292 Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2266 Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2483 Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2906 Gitlab: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3607 Reviewed-by:
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Rhys Perry authored
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Rhys Perry authored
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Rhys Perry authored
Fixes artifacts on decals in Path of Exile. Signed-off-by:
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Rhys Perry authored
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Alyssa Rosenzweig authored
And fix the bad assertion that let this slip. Like combines, nir_op_vec can be vector, and we need to lower this ourselves. Thankfully, the lowering is simple. Fixes dEQP-GLES2.functional.shaders.loops.for_uniform_iterations.nested_tricky_dataflow_1_* Fixes: b2c6cf2b ("pan/bi: Eliminate writemasks in the IR") Signed-off-by:
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Nanley Chery authored
Fixes rendering corruption in the shadowmappingcascade Sascha Willems Vulkan demo. To see the corruption, I adjusted the demo options as follows: 1. Enable "Display depth map" 2. Set "Split lambda" to 0.100 3. Make "Cascade" non-zero. Fixes: 80ffbe91 ("anv: Add support for HiZ+CCS") Reviewed-by:
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Jason Ekstrand authored
In 53bfcdee, we added load/store_scratch instructions which deviate a little bit from most memory load/store instructions in that we can't use the normal untyped read/write instructions which can read and write up to a vec4 at a time. Instead, we have to use the DWORD scattered read/write instructions which are scalar. To handle this, we added code to brw_nir_lower_mem_access_bit_sizes to cause them to be scalarized. However, one case was missing: the load-as-larger-vector case. In this case, we take small bit-sized constant-offset loads replace it with a 32-bit load and shuffle the result around as needed. For scratch, this case is much trickier to get right because it often emits vec2 or wider which we would then have to lower again. We did this for other load and store ops because, for lower bit-sizes we have to scalarize thanks to the byte scattered read/write instructions being scalar. However, for scratch we're not losing as much because we can't vectorize 32-bit loads and stores either. It's easier to just disallow it whenever we have to scalarize. Fixes: 53bfcdee "intel/fs: Implement the new load/store_scratch..." Reviewed-by:
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Dylan Baker authored
sys and string are unused, os is needed but not imported fixes: 412472da ("glsl: Add utility to convert text files to C strings") Reviewed-by:
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Lucas Stach authored
Free the dummy texture descriptor BO on context destroy. Fixes: eda73d71 (etnaviv: GC7000: Texture descriptors) Signed-off-by:
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Pierre-Eric Pelloux-Prayer authored
Fixes: 24f2b0a8 ("gallium/video: remove pipe_video_buffer.chroma_format") Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3595 Reviewed-by:
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Nanley Chery authored
When support for multi-slice fast-clears was introduced for color surfaces, an existing optimization for skipping fast-clears was not updated (this optimization assumed single-slice fast-clears). As a result, the driver began to skip multi-layer fast-clears if just the first slice was in the CLEAR state (ignoring the state of the others). A Civilization VI trace was the only workload I found to make use of this optimization and it did so for 2D, non-array textures. Therefore, this fix simply checks that the depth of the clear box is 1. It also moves the single-slice aux-state query closer to the optimization to clarify the need for the depth check. Enables iris to pass a case of the fcc-write-after-clear piglit test, [fast-clear tracking across layers 0 -> 1 -> (0,1)]. Fixes: 393f659e ("iris: Enable fast clears on other miplevels and layers than 0.") Reviewed-by:
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Lionel Landwerlin authored
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Vinson Lee authored
Fix defect reported by Coverity Scan. Dereference before null check (REVERSE_INULL) check_after_deref: Null-checking rsc suggests that it may be null, but it has already been dereferenced on all paths leading to the check. Fixes: 6173cc19 ("freedreno: gallium driver for adreno") Signed-off-by:
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Jason Ekstrand authored
When I copied and pasted the code from MOV_INDIRECT for handling the dependency controls, I missed a subtle difference between MOV_INDIRECT and SHUFFLE. Specifically, MOV_INDIRECT gets lowered to a narrow instruction on Gen7 by the SIMD width lowering whereas SHUFFLE has to split it in the generator. Therefore, the check safety check for whether or not we can use dependency control has to be based on the lowered width rather than the width of the original instruction. Fixes: a8ac61b0 "intel/fs: NoMask initialize the address..." Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3593 Reviewed-by:
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Bas Nieuwenhuizen authored
The volatile pattern gives me flaky results for 32-bit builds on ChromeOS Android. This is because on 32-bit the volatile 64-bit loads gets split into 2 32-bit loads each. So if we read the lower dword first and then the upper dword, it can happen that the upper dword is already changed but the lower dword isn't yet. In particular for occlusion queries this gives false readings, as the upper dword commonly only constains the ready bit. With the GCC atomic intrinsics we get a call to __atomic_load_8 in libatomic.so which does the right thing. An alternative fix would be to explicitly split the 32-bit loads in the right order and do a bunch of retries if things change, though that gets messy quickly and for 32-bit builds only doesn't feel worth it that much. CC: mesa-stable Reviewed-by:
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Jason Ekstrand authored
Without this, it was checking bit size compatibility with bit sizes such as 96 which is clearly invalid. No shader-db changes on Ice Lake Fixes: ce9205c0 "nir: add a load/store vectorization pass" Reviewed-by:
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Timothy Arceri authored
The linker was adding all state vars as uniforms, doubling the storage size for shaders using only builtin uniforms, which increased CPU overhead for constant buffer uploads. When this code was originally ported from the GLSL IR linker we forgot to exclude builtins because the check was not done in the add_uniform_to_shader class but rather a check was done when passing variables to this class for processing. Fixes: 664e4a61 ("glsl/nir: Fill in the Parameters in NIR linker") Reviewed-by:
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Jason Ekstrand authored
Cc: mesa-stable@lists.freedesktop.org Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2979 Tested-by:
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Anuj Phogat authored
Workaround # 22011374674 Applied to i965, iris and anv drivers No performance impact is observed with WA. Cc: mesa-stable Signed-off-by:
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Marek Olšák authored
After disable SDMA on Arcturus(gfx9), dead lock with aux_context_lock is detected since si_screen_clear_buffer is called recursively before release lock. The call trace is: si_clear_render_target->si_compute_clear_render_target-> si_launch_grid_internal->si_launch_grid->si_emit_cache_flush-> si_prim_discard_signal_next_compute_ib_start->u_suballocator_alloc-> si_resource_create->si_buffer_create->si_alloc_resource-> si_screen_clear_buffer->simple_mtx_lock-> si_sdma_clear_buffer->si_pipe_clear_buffer-> si_clear_buffer->si_compute_do_clear_or_copy-> si_launch_grid_internal->si_launch_grid->si_emit_cache_flush-> si_prim_discard_signal_next_compute_ib_start->u_suballocator_alloc-> si_resource_create->si_buffer_create->si_alloc_resource-> si_screen_clear_buffer->simple_mtx_lock Fixes: 07a49bf5 "radeonsi: disable SDMA on gfx9" Signed-off-by:
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Jason Ekstrand authored
In the case where end was a instruction-based cursor, we would mix up our blocks and end up with block_begin pointing after the second split. This causes a segfault as the cf_node list walk at the end of the function never terminates properly. There's also a possibility of mix-up if begin is an instruction-based cursor which was found by inspection. Fixes: fc7f2d23 "nir/cf: add new control modification API's" Reviewed-by:
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Eric Engestrom authored
It was already part of the backport of 7568c97d, e7dc7f2a1f7d5a38ec88.
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Eric Engestrom authored
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Eric Engestrom authored
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- Oct 03, 2020
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Guido Gunther authored
Document changes and release 20.1.8-1pureos+librem5.1 See merge request Librem5/mesa!6
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- Oct 02, 2020
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Sebastian Krzyszkowiak authored
etnaviv: Track different pipe_screens based on the file descriptions Closes #5 See merge request Librem5/mesa!4
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Guido Gunther authored
The series file has the ordering. This avoids diff noise when dropping patches. Signed-off-by:
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