x86/bugs: Rename _RDS to _SSBD
Intel collateral will reference the SSB mitigation bit in IA32_SPEC_CTL[2] as SSBD (Speculative Store Bypass Disable). Hence changing it. It is unclear yet what the MSR_IA32_ARCH_CAPABILITIES (0x10a) Bit(4) name is going to be. Following the rename it would be SSBD_NO but that rolls out to Speculative Store Bypass Disable No. Also fixed the missing space in X86_FEATURE_AMD_SSBD. [ tglx: Fixup x86_amd_rds_enable() and rds_tif_to_amd_ls_cfg() as well ] Signed-off-by:Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Signed-off-by:
Thomas Gleixner <tglx@linutronix.de>
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- arch/x86/include/asm/cpufeatures.h 2 additions, 2 deletionsarch/x86/include/asm/cpufeatures.h
- arch/x86/include/asm/msr-index.h 5 additions, 5 deletionsarch/x86/include/asm/msr-index.h
- arch/x86/include/asm/spec-ctrl.h 6 additions, 6 deletionsarch/x86/include/asm/spec-ctrl.h
- arch/x86/include/asm/thread_info.h 3 additions, 3 deletionsarch/x86/include/asm/thread_info.h
- arch/x86/kernel/cpu/amd.c 7 additions, 7 deletionsarch/x86/kernel/cpu/amd.c
- arch/x86/kernel/cpu/bugs.c 18 additions, 18 deletionsarch/x86/kernel/cpu/bugs.c
- arch/x86/kernel/cpu/common.c 1 addition, 1 deletionarch/x86/kernel/cpu/common.c
- arch/x86/kernel/cpu/intel.c 1 addition, 1 deletionarch/x86/kernel/cpu/intel.c
- arch/x86/kernel/process.c 4 additions, 4 deletionsarch/x86/kernel/process.c
- arch/x86/kvm/cpuid.c 1 addition, 1 deletionarch/x86/kvm/cpuid.c
- arch/x86/kvm/vmx.c 3 additions, 3 deletionsarch/x86/kvm/vmx.c
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