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Commit bd9862a7 authored by Guido Gunther's avatar Guido Gunther :zzz: Committed by Angus Ainslie (Purism)
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drm_fourcc+dcss: Drop unneded formats from vendor kernel 


We don't have anything feeding these and they cause trouble when
rebasing on linux-next so drop them.

Signed-off-by: default avatarGuido Günther <guido.gunther@puri.sm>
parent e90092c0
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with 14 additions and 98 deletions
drivers/gpu/drm/imx/dcss/dcss-crtc.c
+ 1
− 7
View file @ bd9862a7
......@@ -191,13 +191,7 @@ void dcss_crtc_setup_opipe(struct drm_crtc *crtc, struct drm_connector *conn,
vic = drm_match_cea_mode(&crtc->state->adjusted_mode);
/* FIXME: we should get the connector colorspace some other way */
if (vic == 97 &&
(di->color_formats & DRM_COLOR_FORMAT_YCRCB420) &&
(di->bpc >= 10))
dcss_crtc->opipe_pix_format = DRM_FORMAT_P010;
else
dcss_crtc->opipe_pix_format = DRM_FORMAT_ARGB8888;
dcss_crtc->opipe_pix_format = DRM_FORMAT_ARGB8888;
DRM_INFO("OPIPE_CFG: gamut = %d, nl = %d, pr = %d, pix_format = %s",
dcss_crtc->opipe_g, dcss_crtc->opipe_nl,
......
drivers/gpu/drm/imx/dcss/dcss-plane.c
+ 3
− 19
View file @ bd9862a7
......@@ -54,13 +54,9 @@ static const u32 dcss_common_formats[] = {
/* YUV420 */
DRM_FORMAT_NV12,
DRM_FORMAT_NV21,
DRM_FORMAT_P010,
};
static const u64 dcss_video_format_modifiers[] = {
DRM_FORMAT_MOD_VSI_G1_TILED,
DRM_FORMAT_MOD_VSI_G2_TILED,
DRM_FORMAT_MOD_VSI_G2_TILED_COMPRESSED,
DRM_FORMAT_MOD_INVALID,
};
......@@ -144,12 +140,6 @@ static bool dcss_plane_format_mod_supported(struct drm_plane *plane,
break;
case DRM_PLANE_TYPE_OVERLAY:
switch (format) {
case DRM_FORMAT_NV12:
case DRM_FORMAT_NV21:
case DRM_FORMAT_P010:
return modifier == DRM_FORMAT_MOD_VSI_G1_TILED ||
modifier == DRM_FORMAT_MOD_VSI_G2_TILED ||
modifier == DRM_FORMAT_MOD_VSI_G2_TILED_COMPRESSED;
default:
return false;
}
......@@ -292,8 +282,7 @@ static void dcss_plane_atomic_set_base(struct dcss_plane *dcss_plane)
case DRM_PLANE_TYPE_OVERLAY:
if (!modifiers_present ||
(pix_format != DRM_FORMAT_NV12 &&
pix_format != DRM_FORMAT_NV21 &&
pix_format != DRM_FORMAT_P010)) {
pix_format != DRM_FORMAT_NV21)) {
dcss_dtrc_bypass(dcss_plane->dcss, dcss_plane->ch_num);
return;
}
......@@ -439,13 +428,8 @@ static void dcss_plane_atomic_update(struct drm_plane *plane,
src_w, src_h, adj_w, adj_h);
dcss_plane_atomic_set_base(dcss_plane);
if (fb->modifier == DRM_FORMAT_MOD_VSI_G2_TILED_COMPRESSED) {
scaler_w = src.x1 ? adj_w : src_w;
scaler_h = src.y1 ? adj_h : src_h;
} else {
scaler_w = src_w;
scaler_h = src_h;
}
scaler_w = src_w;
scaler_h = src_h;
dcss_scaler_setup(dcss_plane->dcss, dcss_plane->ch_num,
pixel_format, scaler_w, scaler_h,
......
drivers/gpu/imx/dcss/dcss-common.c
+ 0
− 1
View file @ bd9862a7
......@@ -98,7 +98,6 @@ enum dcss_color_space dcss_drm_fourcc_to_colorspace(u32 drm_fourcc)
case DRM_FORMAT_NV21:
case DRM_FORMAT_NV16:
case DRM_FORMAT_NV61:
case DRM_FORMAT_P010:
return DCSS_COLORSPACE_YUV;
default:
return DCSS_COLORSPACE_UNKNOWN;
......
drivers/gpu/imx/dcss/dcss-dpr.c
+ 1
− 10
View file @ bd9862a7
......@@ -239,9 +239,6 @@ static u32 dcss_dpr_x_pix_wide_adjust(struct dcss_dpr_ch *ch, u32 pix_wide,
pix_in_64byte = pix_in_64byte_map[ch->pix_size][ch->tile];
if (pix_format == DRM_FORMAT_P010)
pix_wide = pix_wide * 10 / 8;
div_64byte_mod = pix_wide % pix_in_64byte;
offset = (div_64byte_mod == 0) ? 0 : (pix_in_64byte - div_64byte_mod);
......@@ -271,13 +268,9 @@ void dcss_dpr_set_res(struct dcss_soc *dcss, int ch_num, u32 xres, u32 yres,
u32 pix_format = dpr->ch[ch_num].pix_format;
if (pix_format == DRM_FORMAT_NV12 ||
pix_format == DRM_FORMAT_NV21 ||
pix_format == DRM_FORMAT_P010)
pix_format == DRM_FORMAT_NV21)
max_planes = 2;
if (pix_format == DRM_FORMAT_P010)
adj_w = adj_w * 10 / 8;
for (plane = 0; plane < max_planes; plane++) {
yres = plane == 1 ? yres >> 1 : yres;
......@@ -486,7 +479,6 @@ static void dcss_dpr_rtram_set(struct dcss_soc *dcss, int ch_num,
switch (pix_format) {
case DRM_FORMAT_NV21:
case DRM_FORMAT_NV12:
case DRM_FORMAT_P010:
ch->rtram_3buf_en = 1;
ch->rtram_4line_en = 0;
break;
......@@ -567,7 +559,6 @@ static int dcss_dpr_get_bpp(u32 pix_format)
switch (pix_format) {
case DRM_FORMAT_NV12:
case DRM_FORMAT_NV21:
case DRM_FORMAT_P010:
bpp = 8;
break;
......
drivers/gpu/imx/dcss/dcss-dtg.c
+ 1
− 7
View file @ bd9862a7
......@@ -304,8 +304,7 @@ static bool dcss_dtg_global_alpha_needed(u32 pix_format)
pix_format == DRM_FORMAT_YUYV ||
pix_format == DRM_FORMAT_YVYU ||
pix_format == DRM_FORMAT_NV12 ||
pix_format == DRM_FORMAT_NV21 ||
pix_format == DRM_FORMAT_P010;
pix_format == DRM_FORMAT_NV21;
}
bool dcss_dtg_global_alpha_changed(struct dcss_soc *dcss, int ch_num,
......@@ -353,11 +352,6 @@ void dcss_dtg_css_set(struct dcss_soc *dcss, u32 pix_format)
{
struct dcss_dtg_priv *dtg = dcss->dtg_priv;
if (pix_format == DRM_FORMAT_P010) {
dtg->control_status &= ~CSS_PIX_COMP_SWAP_MASK;
return;
}
dtg->control_status |=
(0x5 << CSS_PIX_COMP_SWAP_POS) & CSS_PIX_COMP_SWAP_MASK;
}
......
drivers/gpu/imx/dcss/dcss-dtrc.c
+ 5
− 32
View file @ bd9862a7
......@@ -304,20 +304,6 @@ void dcss_dtrc_addr_set(struct dcss_soc *dcss, int ch_num, u32 p1_ba, u32 p2_ba,
dcss_dtrc_write(dtrc, ch_num, p1_ba, DTRC_F1_OFS + DCSS_DTRC_DYDSADDR);
dcss_dtrc_write(dtrc, ch_num, p2_ba, DTRC_F1_OFS + DCSS_DTRC_DCDSADDR);
if (ch->format_modifier == DRM_FORMAT_MOD_VSI_G2_TILED_COMPRESSED) {
ch->y_dec_ofs = dec_table_ofs & 0xFFFFFFFF;
ch->uv_dec_ofs = dec_table_ofs >> 32;
dcss_dtrc_write(dtrc, ch_num, p1_ba + ch->y_dec_ofs,
DCSS_DTRC_DYTSADDR);
dcss_dtrc_write(dtrc, ch_num, p1_ba + ch->uv_dec_ofs,
DCSS_DTRC_DCTSADDR);
dcss_dtrc_write(dtrc, ch_num, p1_ba + ch->y_dec_ofs,
DTRC_F1_OFS + DCSS_DTRC_DYTSADDR);
dcss_dtrc_write(dtrc, ch_num, p1_ba + ch->uv_dec_ofs,
DTRC_F1_OFS + DCSS_DTRC_DCTSADDR);
}
dtrc->ch[ch_num].bypass = false;
}
EXPORT_SYMBOL(dcss_dtrc_addr_set);
......@@ -345,7 +331,7 @@ void dcss_dtrc_set_res(struct dcss_soc *dcss, int ch_num, struct drm_rect *src,
ch->pix_format = pixel_format;
pix_depth = ch->pix_format == DRM_FORMAT_P010 ? 10 : 8;
pix_depth = 8;
old_xres = old_src->x2 - old_src->x1;
old_yres = old_src->y2 - old_src->y1;
xres = src->x2 - src->x1;
......@@ -365,7 +351,7 @@ void dcss_dtrc_set_res(struct dcss_soc *dcss, int ch_num, struct drm_rect *src,
* - 128 pixels for width (8-bit) or 256 (10-bit);
* - 8 lines for height;
*/
width_align = ch->pix_format == DRM_FORMAT_P010 ? 0xff : 0x7f;
width_align = 0x7f;
if (xres == old_xres && !(xres & width_align) &&
yres == old_yres && !(yres & 0xf)) {
ch->dctl &= ~CROPPING_EN;
......@@ -373,15 +359,8 @@ void dcss_dtrc_set_res(struct dcss_soc *dcss, int ch_num, struct drm_rect *src,
}
/* align the image size: down align for compressed formats */
if (ch->format_modifier == DRM_FORMAT_MOD_VSI_G2_TILED_COMPRESSED && src->x1)
xres = xres & ~width_align;
else
xres = (xres - 1 + width_align) & ~width_align;
if (ch->format_modifier == DRM_FORMAT_MOD_VSI_G2_TILED_COMPRESSED && src->y1)
yres = yres & ~0xf;
else
yres = (yres - 1 + 0xf) & ~0xf;
xres = (xres - 1 + width_align) & ~width_align;
yres = (yres - 1 + 0xf) & ~0xf;
src->x1 &= ~1;
src->x2 &= ~1;
......@@ -469,19 +448,13 @@ void dcss_dtrc_enable(struct dcss_soc *dcss, int ch_num, bool enable)
((0xF << TABLE_DATA_SWAP_POS) & TABLE_DATA_SWAP_MASK) |
((0x10 << BURST_LENGTH_POS) & BURST_LENGTH_MASK);
if (ch->format_modifier == DRM_FORMAT_MOD_VSI_G1_TILED)
dtctrl |= G1_TILED_DATA_EN;
dcss_dtrc_write(dtrc, ch_num, dtctrl, DCSS_DTRC_DTCTRL);
curr_frame = dcss_readl(ch->base_reg + DCSS_DTRC_DTCTRL) >> 31;
fdctl = ch->dctl & ~(PIX_DEPTH_8BIT_EN | COMPRESSION_DIS);
fdctl |= ch->pix_format == DRM_FORMAT_P010 ? 0 : PIX_DEPTH_8BIT_EN;
if (ch->format_modifier != DRM_FORMAT_MOD_VSI_G2_TILED_COMPRESSED)
fdctl |= COMPRESSION_DIS;
fdctl |= ch->pix_format == PIX_DEPTH_8BIT_EN;
dcss_dtrc_write(dtrc, ch_num, fdctl,
(curr_frame ^ 1) * DTRC_F1_OFS + DCSS_DTRC_DCTL);
......
drivers/gpu/imx/dcss/dcss-hdr10.c
+ 0
− 4
View file @ bd9862a7
......@@ -579,10 +579,6 @@ static u32 dcss_hdr10_get_bpc(u32 pix_format)
bpc = 8;
break;
case DRM_FORMAT_P010:
bpc = 10;
break;
default:
drm_fb_get_bpp_depth(pix_format, &depth, &bpp);
bpc = depth == 30 ? 10 : 8;
......
drivers/gpu/imx/dcss/dcss-scaler.c
+ 3
− 9
View file @ bd9862a7
......@@ -297,8 +297,7 @@ static void dcss_scaler_res_set(struct dcss_soc *dcss, int ch_num,
pix_format == DRM_FORMAT_YUYV || pix_format == DRM_FORMAT_YVYU)
csrc_xres >>= 1;
else if (pix_format == DRM_FORMAT_NV12 ||
pix_format == DRM_FORMAT_NV21 ||
pix_format == DRM_FORMAT_P010) {
pix_format == DRM_FORMAT_NV21) {
csrc_xres >>= 1;
csrc_yres >>= 1;
}
......@@ -357,8 +356,7 @@ static bool dcss_scaler_fractions_set(struct dcss_soc *dcss, int ch_num,
pix_format == DRM_FORMAT_YUYV || pix_format == DRM_FORMAT_YVYU) {
c_hinc >>= 1;
} else if (pix_format == DRM_FORMAT_NV12 ||
pix_format == DRM_FORMAT_NV21 ||
pix_format == DRM_FORMAT_P010) {
pix_format == DRM_FORMAT_NV21) {
c_hinc >>= 1;
c_vinc >>= 1;
}
......@@ -611,8 +609,7 @@ void dcss_scaler_setup(struct dcss_soc *dcss, int ch_num, u32 pix_format,
dcss_scaler_yuv_enable(dcss, ch_num, true);
if (pix_format == DRM_FORMAT_NV12 ||
pix_format == DRM_FORMAT_NV21 ||
pix_format == DRM_FORMAT_P010) {
pix_format == DRM_FORMAT_NV21) {
rtr_8line_en = true;
src_format = BUF_FMT_YUV420;
} else if (pix_format == DRM_FORMAT_UYVY ||
......@@ -625,9 +622,6 @@ void dcss_scaler_setup(struct dcss_soc *dcss, int ch_num, u32 pix_format,
if (pix_format != ch->pix_format)
dcss_scaler_yuv_coef_set(dcss, ch_num);
if (pix_format == DRM_FORMAT_P010)
pixel_depth = 30;
} else if (dcss_cs == DCSS_COLORSPACE_RGB) {
dcss_scaler_yuv_enable(dcss, ch_num, false);
......
drivers/gpu/imx/dcss/dcss-ss.c
+ 0
− 9
View file @ bd9862a7
......@@ -158,15 +158,6 @@ void dcss_ss_exit(struct dcss_soc *dcss)
void dcss_ss_subsam_set(struct dcss_soc *dcss, u32 pix_format)
{
if (pix_format == DRM_FORMAT_P010) {
dcss_ss_write(dcss->ss_priv, 0x21612161, DCSS_SS_COEFF);
dcss_ss_write(dcss->ss_priv, 2, DCSS_SS_MODE);
dcss_ss_write(dcss->ss_priv, 0x03c00040, DCSS_SS_CLIP_CB);
dcss_ss_write(dcss->ss_priv, 0x03c00040, DCSS_SS_CLIP_CR);
return;
}
dcss_ss_write(dcss->ss_priv, 0x41614161, DCSS_SS_COEFF);
dcss_ss_write(dcss->ss_priv, 0, DCSS_SS_MODE);
dcss_ss_write(dcss->ss_priv, 0x03ff0000, DCSS_SS_CLIP_CB);
......
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