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  1. Dec 11, 2020
  2. Nov 26, 2020
  3. Nov 25, 2020
  4. Nov 19, 2020
    • Maxime Ripard's avatar
      dt-bindings: display: Add a property to deal with WiFi coexistence · 8d15aa4e
      Maxime Ripard authored
      
      The RaspberryPi4 has both a WiFi chip and HDMI outputs capable of doing
      4k. Unfortunately, the 1440p resolution at 60Hz has a TMDS rate on the
      HDMI cable right in the middle of the first Wifi channel.
      
      Add a property to our HDMI controller, that could be reused by other
      similar HDMI controllers, to allow the OS to take whatever measure is
      necessary to avoid that crosstalk.
      
      Signed-off-by: default avatarMaxime Ripard <maxime@cerno.tech>
      Reviewed-by: default avatarNicolas Saenz Julienne <nsaenzjulienne@suse.de>
      Reviewed-by: default avatarRob Herring <robh@kernel.org>
      Link: https://patchwork.freedesktop.org/patch/msgid/20201029134018.1948636-1-maxime@cerno.tech
      8d15aa4e
    • Nicholas Piggin's avatar
      powerpc/64s: flush L1D after user accesses · 9a32a7e7
      Nicholas Piggin authored
      
      IBM Power9 processors can speculatively operate on data in the L1 cache
      before it has been completely validated, via a way-prediction mechanism. It
      is not possible for an attacker to determine the contents of impermissible
      memory using this method, since these systems implement a combination of
      hardware and software security measures to prevent scenarios where
      protected data could be leaked.
      
      However these measures don't address the scenario where an attacker induces
      the operating system to speculatively execute instructions using data that
      the attacker controls. This can be used for example to speculatively bypass
      "kernel user access prevention" techniques, as discovered by Anthony
      Steinhauser of Google's Safeside Project. This is not an attack by itself,
      but there is a possibility it could be used in conjunction with
      side-channels or other weaknesses in the privileged code to construct an
      attack.
      
      This issue can be mitigated by flushing the L1 cache between privilege
      boundaries of concern. This patch flushes the L1 cache after user accesses.
      
      This is part of the fix for CVE-2020-4788.
      
      Signed-off-by: default avatarNicholas Piggin <npiggin@gmail.com>
      Signed-off-by: default avatarDaniel Axtens <dja@axtens.net>
      Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
      9a32a7e7
    • Nicholas Piggin's avatar
      powerpc/64s: flush L1D on kernel entry · f7964378
      Nicholas Piggin authored
      
      IBM Power9 processors can speculatively operate on data in the L1 cache
      before it has been completely validated, via a way-prediction mechanism. It
      is not possible for an attacker to determine the contents of impermissible
      memory using this method, since these systems implement a combination of
      hardware and software security measures to prevent scenarios where
      protected data could be leaked.
      
      However these measures don't address the scenario where an attacker induces
      the operating system to speculatively execute instructions using data that
      the attacker controls. This can be used for example to speculatively bypass
      "kernel user access prevention" techniques, as discovered by Anthony
      Steinhauser of Google's Safeside Project. This is not an attack by itself,
      but there is a possibility it could be used in conjunction with
      side-channels or other weaknesses in the privileged code to construct an
      attack.
      
      This issue can be mitigated by flushing the L1 cache between privilege
      boundaries of concern. This patch flushes the L1 cache on kernel entry.
      
      This is part of the fix for CVE-2020-4788.
      
      Signed-off-by: default avatarNicholas Piggin <npiggin@gmail.com>
      Signed-off-by: default avatarDaniel Axtens <dja@axtens.net>
      Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
      f7964378
  5. Nov 16, 2020
    • Max Filippov's avatar
      xtensa: fix TLBTEMP area placement · 481535c5
      Max Filippov authored
      
      fast_second_level_miss handler for the TLBTEMP area has an assumption
      that page table directory entry for the TLBTEMP address range is 0. For
      it to be true the TLBTEMP area must be aligned to 4MB boundary and not
      share its 4MB region with anything that may use a page table. This is
      not true currently: TLBTEMP shares space with vmalloc space which
      results in the following kinds of runtime errors when
      fast_second_level_miss loads page table directory entry for the vmalloc
      space instead of fixing up the TLBTEMP area:
      
       Unable to handle kernel paging request at virtual address c7ff0e00
        pc = d0009275, ra = 90009478
       Oops: sig: 9 [#1] PREEMPT
       CPU: 1 PID: 61 Comm: kworker/u9:2 Not tainted 5.10.0-rc3-next-20201110-00007-g1fe4962fa983-dirty #58
       Workqueue: xprtiod xs_stream_data_receive_workfn
       a00: 90009478 d11e1dc0 c7ff0e00 00000020 c7ff0000 00000001 7f8b8107 00000000
       a08: 900c5992 d11e1d90 d0cc88b8 5506e97c 00000000 5506e97c d06c8074 d11e1d90
       pc: d0009275, ps: 00060310, depc: 00000014, excvaddr: c7ff0e00
       lbeg: d0009275, lend: d0009287 lcount: 00000003, sar: 00000010
       Call Trace:
         xs_stream_data_receive_workfn+0x43c/0x770
         process_one_work+0x1a1/0x324
         worker_thread+0x1cc/0x3c0
         kthread+0x10d/0x124
         ret_from_kernel_thread+0xc/0x18
      
      Cc: stable@vger.kernel.org
      Signed-off-by: default avatarMax Filippov <jcmvbkbc@gmail.com>
      481535c5
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