• York Sun's avatar
    powerpc/mpc8xxx: Update DDR registers · 57495e4e
    York Sun authored
    DDRC ver 4.7 adds DDR_SLOW bit in sdram_cfg_2 register. This bit needs to be
    set for speed lower than 1250MT/s.
    CDR1 and CDR2 are control driver registers. ODT termination valueis for
    IOs are defined. Starting from DDRC 4.7, the decoding of ODT for IOs is
    	000 -> Termsel off
    	001 -> 120 Ohm
    	010 -> 180 Ohm
    	011 -> 75 Ohm
    	100 -> 110 Ohm
    	101 -> 60 Ohm
    	110 -> 70 Ohm
    	111 -> 47 Ohm
    Add two write leveling registers. Each QDS now has its own write leveling
    start value. In case of zero value, the value of QDS0 will be used. These
    values are board-specific and are set in board files.
    Extend DDR register timing_cfg_1 to have 4 bits for each field.
    DDR control driver registers and write leveling registers are added to
    interactive debugging for easy access.
    Signed-off-by: default avatarYork Sun <yorksun@freescale.com>
    Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
ctrl_regs.c 45.4 KB