• Alexey Brodkin's avatar
    arc: cache - accommodate different L1 cache line lengths · 379b3280
    Alexey Brodkin authored
    ARC core could be configured with different L1 and L2 (AKA SLC) cache
    line lengths. At least these values are possible and were really used:
    32, 64 or 128 bytes.
    
    Current implementation requires cache line to be selected upon U-Boot
    configuration and then it will only work on matching hardware. Indeed
    this is quite efficient because cache line length gets hardcoded during
    code compilation. But OTOH it makes binary less portable.
    
    With this commit we allow U-Boot to determine real L1 cache line length
    early in runtime and use this value later on. This extends portability
    of U-Boot binary a lot.
    Signed-off-by: 's avatarAlexey Brodkin <abrodkin@synopsys.com>
    379b3280
tb100_defconfig 424 Bytes