• Shaveta Leekha's avatar
    powerpc/mpc85xx: Add DSP side awareness for Freescale Heterogeneous SoCs · b8bf0adc
    Shaveta Leekha authored
    The code provides framework for heterogeneous multicore chips based on StarCore
    and Power Architecture which are chasis-2 compliant, like B4860 and B4420
    
    It will make u-boot recognize all non-ppc cores and peripherals like
    SC3900/DSP CPUs, MAPLE, CPRI and print their configuration in u-boot logs.
    Example boot logs of B4860QDS:
    
    U-Boot 2015.01-00232-geef6e36-dirty (Jan 19 2015 - 11:58:45)
    
    CPU0:  B4860E, Version: 2.2, (0x86880022)
    Core:  e6500, Version: 2.0, (0x80400120)
    Clock Configuration:
           CPU0:1600 MHz, CPU1:1600 MHz, CPU2:1600 MHz, CPU3:1600 MHz,
           DSP CPU0:1200 MHz, DSP CPU1:1200 MHz, DSP CPU2:1200 MHz, DSP CPU3:1200 MHz,
           DSP CPU4:1200 MHz, DSP CPU5:1200 MHz,
           CCB:666.667 MHz,
           DDR:933.333 MHz (1866.667 MT/s data rate) (Asynchronous), IFC:166.667 MHz
           CPRI:600  MHz
           MAPLE:600  MHz, MAPLE-ULB:800  MHz, MAPLE-eTVPE:1000 MHz
           FMAN1: 666.667 MHz
           QMAN:  333.333 MHz
    
    Top level changes include:
    (1) Top level CONFIG to identify HETEROGENUOUS clusters
    (2) CONFIGS for SC3900/DSP components
    (3) Global structures like "cpu_type" and "MPC85xx_SYS_INFO"
        updated for dsp cores and other components
    (3) APIs to get DSP num cores and their Mask like:
            cpu_dsp_mask, cpu_num_dspcores etc same as that of PowerPC
    (5) Code to fetch and print SC cores and other heterogenous
        device's frequencies
    (6) README added for the same
    Signed-off-by: default avatarShaveta Leekha <shaveta@freescale.com>
    Reviewed-by: default avatarYork Sun <yorksun@freescale.com>
    b8bf0adc
README.Heterogeneous-SoCs 3.58 KB