• Aneesh V's avatar
    armv7: omap3: leave outer cache enabled · f1f2c3ca
    Aneesh V authored
    Mainline kernel for OMAP3 doesn't enable L2 cache
    It expects L2$ to be enabled by ROM-code/bootloader.
    
    Leaving L2$ enabled can be troublesome in cases where
    the L2 cache is not under CP15 control, such as in
    Cortex-A9. This problem is explained in detail in
    the commit dc7100f4
    
    However, this problem doesn't apply to Cortex-A8
    because L2$ in Cortex-A8 is under CP15 control and
    hence the generic armv7 maintenance opertions work
    for it.
    
    As such we can make an exception for OMAP3 and
    leave the L2$ enabled when we jump to kernel. This
    is done by removing the strongly-linked implementation
    of v7_outer_cache_disable() and allowing it to fall
    back to the weakly linked implementation that doesn't
    do anything.
    Signed-off-by: default avatarAneesh V <aneesh@ti.com>
    f1f2c3ca
board.c 12.6 KB