• Ye.Li's avatar
    MLK-10647 armv7: Fix Dcache disable issue on i.MX7 · 3eaf5649
    Ye.Li authored
    The issue on the i.MX7D is that, there is one cache-able memory access
    between the L1 and L2 cache flush by calling the flush_dache_all->
    v7_maint_dcache_all() [Flush L1 and L2 cache) which written in the C code.
    
    L1-cache-flush            -> This will flush L1 cache to L2 cache in the end.
    Cache-able memory access  -> This will have the chance cause the L1 line-fill
                                 with dirty data from L2 cache(L1 cache-line dirty,
                                 L2 clean)
    L2-cache-flush            -> This will only flush L2 cache to L3, but still
                                 some dirty data on the L1 cacheline.
    
    After C & M bit clean,    -> The dirty data on the L1 cache line lost, which will
                                 cause memory coherent issue if that dirty cache line
                                 has some useful data
    
    The only problem here is: there is one cache-cable memory access between L1 and L2 cache flush.
    
    This patch should works fine on the i.MX6 and i.MX7.
    
    The second cache flush have zero impact on the i.MX6, but this is really need for
    the i.MX7D platform due to the L1 line-fill during the first dcache_flush.
    
    And the second flush will not bring in the L1 dirty cache line due to the C bit is
    clear now, which means the dcache is disabled.
    
    Acked-by: Jason Liu<r64343@freescale.com>
    Reviewed-by: Jason Liu<r64343@freescale.com>
    Signed-off-by: 's avatarYe.Li <B37916@freescale.com>
    (cherry picked from commit f5d5f07fba936c4bb05c887de9d72fb75b3dc0f2)
    (cherry picked from commit 86c784cf4c4b633d37a76de7d47155c08f75dc82)
    (cherry picked from commit d85cd484e6825631aa1ab572e5e0539f2191d795)
    (cherry picked from commit 2b29c1873c2293abe1c4b361392521223b9c9ecf)
    3eaf5649
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