• Fabio Estevam's avatar
    mx6: ddr: Allow changing REFSEL and REFR fields · edf00937
    Fabio Estevam authored
    Currently MX6 SPL DDR initialization hardcodes the REF_SEL and
    REFR fields of the MDREF register as 1 and 7, respectively for
    DDR3 and 0 and 3 for LPDDR2.
    
    Looking at the MDREF initialization done via DCD we see that
    boards do need to initialize these fields differently:
    
    $ git grep 0x021b0020 board/
    board/bachmann/ot1200/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800
    board/ccv/xpress/imximage.cfg:DATA 4 0x021b0020 0x00000800 /* MMDC0_MDREF */
    board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x7800
    board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x00005800
    board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800
    board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800
    board/freescale/mx6qsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00005800
    board/freescale/mx6qsabreauto/mx6dl.cfg:DATA 4 0x021b0020 0x00005800
    board/freescale/mx6qsabreauto/mx6qp.cfg:DATA 4 0x021b0020 0x00005800
    board/freescale/mx6sabresd/mx6dlsabresd.cfg:DATA 4      0x021b0020 0x00005800
    board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800
    board/freescale/mx6slevk/imximage.cfg:DATA 4 0x021b0020 0x00001800
    board/freescale/mx6sxsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00000800
    board/freescale/mx6sxsabresd/imximage.cfg:DATA 4 0x021b0020 0x00000800
    board/warp/imximage.cfg:DATA 4 0x021b0020 0x00001800
    
    So introduce a mechanism for users to be able to configure
    REFSEL and REFR fields as needed.
    
    Keep all the mx6 SPL users in their current REF_SEL and REFR values,
    so no functional changes for the existing users.
    Signed-off-by: 's avatarFabio Estevam <fabio.estevam@nxp.com>
    Reviewed-by: 's avatarEric Nelson <eric@nelint.com>
    edf00937
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