• Paul Gortmaker's avatar
    sbc8548: Fix up local bus init to be frequency aware · e2b363ff
    Paul Gortmaker authored
    The code here was copied from the mpc8548cds support, and it
    wasn't using the CONFIG_SYS_LBC_LCRR define, and was just
    unconditionally setting the LCRR_EADC bit.  Snooping with a
    hardware debugger also showed we had LCRR_DBYP set, since we were
    setting it based on a read of an uninitialized lcrr read via
    clkdiv.  Borrow from the code in the tqm85xx.c support to add
    LBC frequency aware masking of these bits.
    
    This change will correct reliability issues associated with trying
    to use the 128MB of LBC 100MHz SDRAM on this board.  Thanks to
    Keith Savage for assistance in diagnosing the root cause of this.
    Signed-off-by: default avatarPaul Gortmaker <paul.gortmaker@windriver.com>
    Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
    e2b363ff
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