• Joel Stanley's avatar
    clk: aspeed: Support HPLL strapping on ast2400 · 565b9937
    Joel Stanley authored
    The HPLL can be configured through a register (SCU24), however some
    platforms chose to configure it through the strapping settings and do
    not use the register. This was not noticed as the logic for bit 18 in
    SCU24 was confused: set means programmed, but the driver read it as set
    means strapped.
    
    This gives us the correct HPLL value on Palmetto systems, from which
    most of the peripheral clocks are generated.
    
    Fixes: 5eda5d79 ("clk: Add clock driver for ASPEED BMC SoCs")
    Cc: stable@vger.kernel.org # v4.15
    Reviewed-by: default avatarCédric Le Goater <clg@kaod.org>
    Signed-off-by: default avatarJoel Stanley <joel@jms.id.au>
    Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
    565b9937
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